fpr.c
1 /*
2 * Floating-point operations.
3 *
4 * This file implements the non-inline functions declared in
5 * fpr.h, as well as the constants for FFT / iFFT.
6 *
7 * ==========================(LICENSE BEGIN)============================
8 *
9 * Copyright (c) 2017-2019 Falcon Project
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining
12 * a copy of this software and associated documentation files (the
13 * "Software"), to deal in the Software without restriction, including
14 * without limitation the rights to use, copy, modify, merge, publish,
15 * distribute, sublicense, and/or sell copies of the Software, and to
16 * permit persons to whom the Software is furnished to do so, subject to
17 * the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be
20 * included in all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
26 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 *
30 * ===========================(LICENSE END)=============================
31 *
32 * @author Thomas Pornin <thomas.pornin@nccgroup.com>
33 */
34
35 #include "inner.h"
36
37 #if FALCON_FPEMU // yyyFPEMU+1
38
39 /*
40 * Normalize a provided unsigned integer to the 2^63..2^64-1 range by
41 * left-shifting it if necessary. The exponent e is adjusted accordingly
42 * (i.e. if the value was left-shifted by n bits, then n is subtracted
43 * from e). If source m is 0, then it remains 0, but e is altered.
44 * Both m and e must be simple variables (no expressions allowed).
45 */
46 #define FPR_NORM64(m, e) do { \
47 uint32_t nt; \
48 \
49 (e) -= 63; \
50 \
51 nt = (uint32_t)((m) >> 32); \
52 nt = (nt | -nt) >> 31; \
53 (m) ^= ((m) ^ ((m) << 32)) & ((uint64_t)nt - 1); \
54 (e) += (int)(nt << 5); \
55 \
56 nt = (uint32_t)((m) >> 48); \
57 nt = (nt | -nt) >> 31; \
58 (m) ^= ((m) ^ ((m) << 16)) & ((uint64_t)nt - 1); \
59 (e) += (int)(nt << 4); \
60 \
61 nt = (uint32_t)((m) >> 56); \
62 nt = (nt | -nt) >> 31; \
63 (m) ^= ((m) ^ ((m) << 8)) & ((uint64_t)nt - 1); \
64 (e) += (int)(nt << 3); \
65 \
66 nt = (uint32_t)((m) >> 60); \
67 nt = (nt | -nt) >> 31; \
68 (m) ^= ((m) ^ ((m) << 4)) & ((uint64_t)nt - 1); \
69 (e) += (int)(nt << 2); \
70 \
71 nt = (uint32_t)((m) >> 62); \
72 nt = (nt | -nt) >> 31; \
73 (m) ^= ((m) ^ ((m) << 2)) & ((uint64_t)nt - 1); \
74 (e) += (int)(nt << 1); \
75 \
76 nt = (uint32_t)((m) >> 63); \
77 (m) ^= ((m) ^ ((m) << 1)) & ((uint64_t)nt - 1); \
78 (e) += (int)(nt); \
79 } while (0)
80
81 #if FALCON_ASM_CORTEXM4 // yyyASM_CORTEXM4+1
82
83 __attribute__((naked))
84 fpr
85 fpr_scaled(int64_t i __attribute__((unused)), int sc __attribute__((unused)))
86 {
87 __asm__ (
88 "push { r4, r5, r6, lr }\n\t"
89 "\n\t"
90 "@ Input i is in r0:r1, and sc in r2.\n\t"
91 "@ Extract the sign bit, and compute the absolute value.\n\t"
92 "@ -> sign bit in r3, with value 0 or -1\n\t"
93 "asrs r3, r1, #31\n\t"
94 "eors r0, r3\n\t"
95 "eors r1, r3\n\t"
96 "subs r0, r3\n\t"
97 "sbcs r1, r3\n\t"
98 "\n\t"
99 "@ Scale exponent to account for the encoding; if the source is\n\t"
100 "@ zero or if the scaled exponent is negative, it is set to 32.\n\t"
101 "addw r2, r2, #1022\n\t"
102 "orrs r4, r0, r1\n\t"
103 "bics r4, r4, r2, asr #31\n\t"
104 "rsbs r5, r4, #0\n\t"
105 "orrs r4, r5\n\t"
106 "ands r2, r2, r4, asr #31\n\t"
107 "adds r2, #32\n\t"
108 "\n\t"
109 "@ Normalize value to a full 64-bit width, by shifting it left.\n\t"
110 "@ The shift count is subtracted from the exponent (in r2).\n\t"
111 "@ If the mantissa is 0, the exponent is set to 0.\n\t"
112 "\n\t"
113 "@ If top word is 0, replace with low word; otherwise, add 32 to\n\t"
114 "@ the exponent.\n\t"
115 "rsbs r4, r1, #0\n\t"
116 "orrs r4, r1\n\t"
117 "eors r5, r0, r1\n\t"
118 "bics r5, r5, r4, asr #31\n\t"
119 "eors r1, r5\n\t"
120 "ands r0, r0, r4, asr #31\n\t"
121 "lsrs r4, r4, #31\n\t"
122 "adds r2, r2, r4, lsl #5\n\t"
123 "\n\t"
124 "@ Count leading zeros of r1 to finish the shift.\n\t"
125 "clz r4, r1\n\t"
126 "subs r2, r4\n\t"
127 "rsbs r5, r4, #32\n\t"
128 "lsls r1, r4\n\t"
129 "lsrs r5, r0, r5\n\t"
130 "lsls r0, r4\n\t"
131 "orrs r1, r5\n\t"
132 "\n\t"
133 "@ Clear the top bit; we know it's a 1 (unless the whole mantissa\n\t"
134 "@ was zero, but then it's still OK to clear it)\n\t"
135 "bfc r1, #31, #1\n\t"
136 "\n\t"
137 "@ Now shift right the value by 11 bits; this puts the value in\n\t"
138 "@ the 2^52..2^53-1 range. We also keep a copy of the pre-shift\n\t"
139 "@ low bits in r5.\n\t"
140 "movs r5, r0\n\t"
141 "lsrs r0, #11\n\t"
142 "orrs r0, r0, r1, lsl #21\n\t"
143 "lsrs r1, #11\n\t"
144 "\n\t"
145 "@ Also plug the exponent at the right place. This must be done\n\t"
146 "@ now so that, in case the rounding creates a carry, that carry\n\t"
147 "@ adds to the exponent, which would be exactly what we want at\n\t"
148 "@ that point.\n\t"
149 "orrs r1, r1, r2, lsl #20\n\t"
150 "\n\t"
151 "@ Rounding: we must add 1 to the mantissa in the following cases:\n\t"
152 "@ - bits 11 to 9 of r5 are '011', '110' or '111'\n\t"
153 "@ - bits 11 to 9 of r5 are '010' and one of the\n\t"
154 "@ bits 0 to 8 is non-zero\n\t"
155 "ubfx r6, r5, #0, #9\n\t"
156 "addw r6, r6, #511\n\t"
157 "orrs r5, r6\n\t"
158 "\n\t"
159 "ubfx r5, r5, #9, #3\n\t"
160 "movs r6, #0xC8\n\t"
161 "lsrs r6, r5\n\t"
162 "ands r6, #1\n\t"
163 "adds r0, r6\n\t"
164 "adcs r1, #0\n\t"
165 "\n\t"
166 "@ Put back the sign.\n\t"
167 "orrs r1, r1, r3, lsl #31\n\t"
168 "\n\t"
169 "pop { r4, r5, r6, pc}\n\t"
170 );
171 }
172
173 #else // yyyASM_CORTEXM4+0
174
175 fpr
176 fpr_scaled(int64_t i, int sc)
177 {
178 /*
179 * To convert from int to float, we have to do the following:
180 * 1. Get the absolute value of the input, and its sign
181 * 2. Shift right or left the value as appropriate
182 * 3. Pack the result
183 *
184 * We can assume that the source integer is not -2^63.
185 */
186 int s, e;
187 uint32_t t;
188 uint64_t m;
189
190 /*
191 * Extract sign bit.
192 * We have: -i = 1 + ~i
193 */
194 s = (int)((uint64_t)i >> 63);
195 i ^= -(int64_t)s;
196 i += s;
197
198 /*
199 * For now we suppose that i != 0.
200 * Otherwise, we set m to i and left-shift it as much as needed
201 * to get a 1 in the top bit. We can do that in a logarithmic
202 * number of conditional shifts.
203 */
204 m = (uint64_t)i;
205 e = 9 + sc;
206 FPR_NORM64(m, e);
207
208 /*
209 * Now m is in the 2^63..2^64-1 range. We must divide it by 512;
210 * if one of the dropped bits is a 1, this should go into the
211 * "sticky bit".
212 */
213 m |= ((uint32_t)m & 0x1FF) + 0x1FF;
214 m >>= 9;
215
216 /*
217 * Corrective action: if i = 0 then all of the above was
218 * incorrect, and we clamp e and m down to zero.
219 */
220 t = (uint32_t)((uint64_t)(i | -i) >> 63);
221 m &= -(uint64_t)t;
222 e &= -(int)t;
223
224 /*
225 * Assemble back everything. The FPR() function will handle cases
226 * where e is too low.
227 */
228 return FPR(s, e, m);
229 }
230
231 #endif // yyyASM_CORTEXM4-
232
233 #if FALCON_ASM_CORTEXM4 // yyyASM_CORTEXM4+1
234
235 // yyyPQCLEAN+0
236 #if 0
237 /* Debug code -- To get a printout of registers from a specific point
238 in ARM Cortex M4 assembly code, uncomment this code and add a
239 "bl DEBUG" call where wished for. */
240
241 void
242 print_regs(uint32_t *rr, uint32_t flags)
243 {
244 int i;
245 extern int printf(const char *fmt, ...);
246
247 printf("\nRegs:\n");
248 for (i = 0; i < 7; i ++) {
249 int j;
250
251 j = i + 7;
252 printf(" %2d = %08X %2d = %08X\n", i, rr[i], j, rr[j]);
253 }
254 printf(" flags = %08X ", flags);
255 if ((flags >> 31) & 1) {
256 printf("N");
257 }
258 if ((flags >> 30) & 1) {
259 printf("Z");
260 }
261 if ((flags >> 29) & 1) {
262 printf("C");
263 }
264 if ((flags >> 28) & 1) {
265 printf("V");
266 }
267 if ((flags >> 27) & 1) {
268 printf("Q");
269 }
270 printf("\n");
271 }
272
273 __attribute__((naked))
274 void
275 DEBUG(void)
276 {
277 __asm__ (
278 "push { r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr }\n\t"
279 "mov r0, sp\n\t"
280 "mrs r1, apsr\n\t"
281 "bl print_regs\n\t"
282 "pop { r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, pc }\n\t"
283 );
284 }
285 #endif
286 // yyyPQCLEAN-
287
288 __attribute__((naked))
289 fpr
290 fpr_add(fpr x __attribute__((unused)), fpr y __attribute__((unused)))
291 {
292 __asm__ (
293 "push { r4, r5, r6, r7, r8, r10, r11, lr }\n\t"
294 "\n\t"
295 "@ Make sure that the first operand (x) has the larger absolute\n\t"
296 "@ value. This guarantees that the exponent of y is less than\n\t"
297 "@ or equal to the exponent of x, and, if they are equal, then\n\t"
298 "@ the mantissa of y will not be greater than the mantissa of x.\n\t"
299 "@ However, if absolute values are equal and the sign of x is 1,\n\t"
300 "@ then we want to also swap the values.\n\t"
301 "ubfx r4, r1, #0, #31 @ top word without sign bit\n\t"
302 "ubfx r5, r3, #0, #31 @ top word without sign bit\n\t"
303 "subs r7, r0, r2 @ difference in r7:r4\n\t"
304 "sbcs r4, r5\n\t"
305 "orrs r7, r4\n\t"
306 "rsbs r5, r7, #0\n\t"
307 "orrs r7, r5 @ bit 31 of r7 is 0 iff difference is zero\n\t"
308 "bics r6, r1, r7\n\t"
309 "orrs r6, r4 @ bit 31 of r6 is 1 iff the swap must be done\n\t"
310 "\n\t"
311 "@ Conditional swap\n\t"
312 "eors r4, r0, r2\n\t"
313 "eors r5, r1, r3\n\t"
314 "ands r4, r4, r6, asr #31\n\t"
315 "ands r5, r5, r6, asr #31\n\t"
316 "eors r0, r4\n\t"
317 "eors r1, r5\n\t"
318 "eors r2, r4\n\t"
319 "eors r3, r5\n\t"
320 "\n\t"
321 "@ Extract mantissa of x into r0:r1, exponent in r4, sign in r5\n\t"
322 "ubfx r4, r1, #20, #11 @ Exponent in r4 (without sign)\n\t"
323 "addw r5, r4, #2047 @ Get a carry to test r4 for zero\n\t"
324 "lsrs r5, #11 @ r5 is the mantissa implicit high bit\n\t"
325 "bfc r1, #20, #11 @ Clear exponent bits (not the sign)\n\t"
326 "orrs r1, r1, r5, lsl #20 @ Set mantissa high bit\n\t"
327 "asrs r5, r1, #31 @ Get sign bit (sign-extended)\n\t"
328 "bfc r1, #31, #1 @ Clear the sign bit\n\t"
329 "\n\t"
330 "@ Extract mantissa of y into r2:r3, exponent in r6, sign in r7\n\t"
331 "ubfx r6, r3, #20, #11 @ Exponent in r6 (without sign)\n\t"
332 "addw r7, r6, #2047 @ Get a carry to test r6 for zero\n\t"
333 "lsrs r7, #11 @ r7 is the mantissa implicit high bit\n\t"
334 "bfc r3, #20, #11 @ Clear exponent bits (not the sign)\n\t"
335 "orrs r3, r3, r7, lsl #20 @ Set mantissa high bit\n\t"
336 "asrs r7, r3, #31 @ Get sign bit (sign-extended)\n\t"
337 "bfc r3, #31, #1 @ Clear the sign bit\n\t"
338 "\n\t"
339 "@ Scale mantissas up by three bits.\n\t"
340 "lsls r1, #3\n\t"
341 "orrs r1, r1, r0, lsr #29\n\t"
342 "lsls r0, #3\n\t"
343 "lsls r3, #3\n\t"
344 "orrs r3, r3, r2, lsr #29\n\t"
345 "lsls r2, #3\n\t"
346 "\n\t"
347 "@ x: exponent=r4, sign=r5, mantissa=r0:r1 (scaled up 3 bits)\n\t"
348 "@ y: exponent=r6, sign=r7, mantissa=r2:r3 (scaled up 3 bits)\n\t"
349 "\n\t"
350 "@ At that point, the exponent of x (in r4) is larger than that\n\t"
351 "@ of y (in r6). The difference is the amount of shifting that\n\t"
352 "@ should be done on y. If that amount is larger than 59 then\n\t"
353 "@ we clamp y to 0. We won't need y's exponent beyond that point,\n\t"
354 "@ so we store that shift count in r6.\n\t"
355 "subs r6, r4, r6\n\t"
356 "subs r8, r6, #60\n\t"
357 "ands r2, r2, r8, asr #31\n\t"
358 "ands r3, r3, r8, asr #31\n\t"
359 "\n\t"
360 "@ Shift right r2:r3 by r6 bits. The shift count is in the 0..59\n\t"
361 "@ range. r11 will be non-zero if and only if some non-zero bits\n\t"
362 "@ were dropped.\n\t"
363 "subs r8, r6, #32\n\t"
364 "bics r11, r2, r8, asr #31\n\t"
365 "ands r2, r2, r8, asr #31\n\t"
366 "bics r10, r3, r8, asr #31\n\t"
367 "orrs r2, r2, r10\n\t"
368 "ands r3, r3, r8, asr #31\n\t"
369 "ands r6, r6, #31\n\t"
370 "rsbs r8, r6, #32\n\t"
371 "lsls r10, r2, r8\n\t"
372 "orrs r11, r11, r10\n\t"
373 "lsrs r2, r2, r6\n\t"
374 "lsls r10, r3, r8\n\t"
375 "orrs r2, r2, r10\n\t"
376 "lsrs r3, r3, r6\n\t"
377 "\n\t"
378 "@ If r11 is non-zero then some non-zero bit was dropped and the\n\t"
379 "@ low bit of r2 must be forced to 1 ('sticky bit').\n\t"
380 "rsbs r6, r11, #0\n\t"
381 "orrs r6, r6, r11\n\t"
382 "orrs r2, r2, r6, lsr #31\n\t"
383 "\n\t"
384 "@ x: exponent=r4, sign=r5, mantissa=r0:r1 (scaled up 3 bits)\n\t"
385 "@ y: sign=r7, value=r2:r3 (scaled to same exponent as x)\n\t"
386 "\n\t"
387 "@ If x and y don't have the same sign, then we should negate r2:r3\n\t"
388 "@ (i.e. subtract the mantissa instead of adding it). Signs of x\n\t"
389 "@ and y are in r5 and r7, as full-width words. We won't need r7\n\t"
390 "@ afterwards.\n\t"
391 "eors r7, r5 @ r7 = -1 if y must be negated, 0 otherwise\n\t"
392 "eors r2, r7\n\t"
393 "eors r3, r7\n\t"
394 "subs r2, r7\n\t"
395 "sbcs r3, r7\n\t"
396 "\n\t"
397 "@ r2:r3 has been shifted, we can add to r0:r1.\n\t"
398 "adds r0, r2\n\t"
399 "adcs r1, r3\n\t"
400 "\n\t"
401 "@ result: exponent=r4, sign=r5, mantissa=r0:r1 (scaled up 3 bits)\n\t"
402 "\n\t"
403 "@ Normalize the result with some left-shifting to full 64-bit\n\t"
404 "@ width. Shift count goes to r2, and exponent (r4) is adjusted.\n\t"
405 "clz r2, r0\n\t"
406 "clz r3, r1\n\t"
407 "sbfx r6, r3, #5, #1\n\t"
408 "ands r2, r6\n\t"
409 "adds r2, r2, r3\n\t"
410 "subs r4, r4, r2\n\t"
411 "\n\t"
412 "@ Shift r0:r1 to the left by r2 bits.\n\t"
413 "subs r7, r2, #32\n\t"
414 "lsls r7, r0, r7\n\t"
415 "lsls r1, r1, r2\n\t"
416 "rsbs r6, r2, #32\n\t"
417 "orrs r1, r1, r7\n\t"
418 "lsrs r6, r0, r6\n\t"
419 "orrs r1, r1, r6\n\t"
420 "lsls r0, r0, r2\n\t"
421 "\n\t"
422 "@ The exponent of x was in r4. The left-shift operation has\n\t"
423 "@ subtracted some value from it, 8 in case the result has the\n\t"
424 "@ same exponent as x. However, the high bit of the mantissa will\n\t"
425 "@ add 1 to the exponent, so we only add back 7 (the exponent is\n\t"
426 "@ added in because rounding might have produced a carry, which\n\t"
427 "@ should then spill into the exponent).\n\t"
428 "adds r4, #7\n\t"
429 "\n\t"
430 "@ If the mantissa new mantissa is non-zero, then its bit 63 is\n\t"
431 "@ non-zero (thanks to the normalizing shift). Otherwise, that bit\n\t"
432 "@ is zero, and we should then set the exponent to zero as well.\n\t"
433 "ands r4, r4, r1, asr #31\n\t"
434 "\n\t"
435 "@ Shrink back the value to a 52-bit mantissa. This requires\n\t"
436 "@ right-shifting by 11 bits; we keep a copy of the pre-shift\n\t"
437 "@ low word in r3.\n\t"
438 "movs r3, r0\n\t"
439 "lsrs r0, #11\n\t"
440 "orrs r0, r0, r1, lsl #21\n\t"
441 "lsrs r1, #11\n\t"
442 "\n\t"
443 "@ Apply rounding.\n\t"
444 "ubfx r6, r3, #0, #9\n\t"
445 "addw r6, r6, #511\n\t"
446 "orrs r3, r6\n\t"
447 "ubfx r3, r3, #9, #3\n\t"
448 "movs r6, #0xC8\n\t"
449 "lsrs r6, r3\n\t"
450 "ands r6, #1\n\t"
451 "adds r0, r6\n\t"
452 "adcs r1, #0\n\t"
453 "\n\t"
454 "@Plug in the exponent with an addition.\n\t"
455 "adds r1, r1, r4, lsl #20\n\t"
456 "\n\t"
457 "@ If the new exponent is negative or zero, then it underflowed\n\t"
458 "@ and we must clear the whole mantissa and exponent.\n\t"
459 "rsbs r4, r4, #0\n\t"
460 "ands r0, r0, r4, asr #31\n\t"
461 "ands r1, r1, r4, asr #31\n\t"
462 "\n\t"
463 "@ Put back the sign. This is the sign of x: thanks to the\n\t"
464 "@ conditional swap at the start, this is always correct.\n\t"
465 "bfi r1, r5, #31, #1\n\t"
466 "\n\t"
467 "pop { r4, r5, r6, r7, r8, r10, r11, pc }\n\t"
468 );
469 }
470
471 #else // yyyASM_CORTEXM4+0
472
473 fpr
474 fpr_add(fpr x, fpr y)
475 {
476 uint64_t m, xu, yu, za;
477 uint32_t cs;
478 int ex, ey, sx, sy, cc;
479
480 /*
481 * Make sure that the first operand (x) has the larger absolute
482 * value. This guarantees that the exponent of y is less than
483 * or equal to the exponent of x, and, if they are equal, then
484 * the mantissa of y will not be greater than the mantissa of x.
485 *
486 * After this swap, the result will have the sign x, except in
487 * the following edge case: abs(x) = abs(y), and x and y have
488 * opposite sign bits; in that case, the result shall be +0
489 * even if the sign bit of x is 1. To handle this case properly,
490 * we do the swap is abs(x) = abs(y) AND the sign of x is 1.
491 */
492 m = ((uint64_t)1 << 63) - 1;
493 za = (x & m) - (y & m);
494 cs = (uint32_t)(za >> 63)
495 | ((1U - (uint32_t)(-za >> 63)) & (uint32_t)(x >> 63));
496 m = (x ^ y) & -(uint64_t)cs;
497 x ^= m;
498 y ^= m;
499
500 /*
501 * Extract sign bits, exponents and mantissas. The mantissas are
502 * scaled up to 2^55..2^56-1, and the exponent is unbiased. If
503 * an operand is zero, its mantissa is set to 0 at this step, and
504 * its exponent will be -1078.
505 */
506 ex = (int)(x >> 52);
507 sx = ex >> 11;
508 ex &= 0x7FF;
509 m = (uint64_t)(uint32_t)((ex + 0x7FF) >> 11) << 52;
510 xu = ((x & (((uint64_t)1 << 52) - 1)) | m) << 3;
511 ex -= 1078;
512 ey = (int)(y >> 52);
513 sy = ey >> 11;
514 ey &= 0x7FF;
515 m = (uint64_t)(uint32_t)((ey + 0x7FF) >> 11) << 52;
516 yu = ((y & (((uint64_t)1 << 52) - 1)) | m) << 3;
517 ey -= 1078;
518
519 /*
520 * x has the larger exponent; hence, we only need to right-shift y.
521 * If the shift count is larger than 59 bits then we clamp the
522 * value to zero.
523 */
524 cc = ex - ey;
525 yu &= -(uint64_t)((uint32_t)(cc - 60) >> 31);
526 cc &= 63;
527
528 /*
529 * The lowest bit of yu is "sticky".
530 */
531 m = fpr_ulsh(1, cc) - 1;
532 yu |= (yu & m) + m;
533 yu = fpr_ursh(yu, cc);
534
535 /*
536 * If the operands have the same sign, then we add the mantissas;
537 * otherwise, we subtract the mantissas.
538 */
539 xu += yu - ((yu << 1) & -(uint64_t)(sx ^ sy));
540
541 /*
542 * The result may be smaller, or slightly larger. We normalize
543 * it to the 2^63..2^64-1 range (if xu is zero, then it stays
544 * at zero).
545 */
546 FPR_NORM64(xu, ex);
547
548 /*
549 * Scale down the value to 2^54..s^55-1, handling the last bit
550 * as sticky.
551 */
552 xu |= ((uint32_t)xu & 0x1FF) + 0x1FF;
553 xu >>= 9;
554 ex += 9;
555
556 /*
557 * In general, the result has the sign of x. However, if the
558 * result is exactly zero, then the following situations may
559 * be encountered:
560 * x > 0, y = -x -> result should be +0
561 * x < 0, y = -x -> result should be +0
562 * x = +0, y = +0 -> result should be +0
563 * x = -0, y = +0 -> result should be +0
564 * x = +0, y = -0 -> result should be +0
565 * x = -0, y = -0 -> result should be -0
566 *
567 * But at the conditional swap step at the start of the
568 * function, we ensured that if abs(x) = abs(y) and the
569 * sign of x was 1, then x and y were swapped. Thus, the
570 * two following cases cannot actually happen:
571 * x < 0, y = -x
572 * x = -0, y = +0
573 * In all other cases, the sign bit of x is conserved, which
574 * is what the FPR() function does. The FPR() function also
575 * properly clamps values to zero when the exponent is too
576 * low, but does not alter the sign in that case.
577 */
578 return FPR(sx, ex, xu);
579 }
580
581 #endif // yyyASM_CORTEXM4-
582
583 #if FALCON_ASM_CORTEXM4 // yyyASM_CORTEXM4+1
584
585 __attribute__((naked))
586 fpr
587 fpr_mul(fpr x __attribute__((unused)), fpr y __attribute__((unused)))
588 {
589 __asm__ (
590 "push { r4, r5, r6, r7, r8, r10, r11, lr }\n\t"
591 "\n\t"
592 "@ Extract mantissas: x.m = r4:r5, y.m = r6:r7\n\t"
593 "@ r4 and r6 contain only 25 bits each.\n\t"
594 "bics r4, r0, #0xFE000000\n\t"
595 "lsls r5, r1, #7\n\t"
596 "orrs r5, r5, r0, lsr #25\n\t"
597 "orrs r5, r5, #0x08000000\n\t"
598 "bics r5, r5, #0xF0000000\n\t"
599 "bics r6, r2, #0xFE000000\n\t"
600 "lsls r7, r3, #7\n\t"
601 "orrs r7, r7, r2, lsr #25\n\t"
602 "orrs r7, r7, #0x08000000\n\t"
603 "bics r7, r7, #0xF0000000\n\t"
604 "\n\t"
605 "@ Perform product. Values are in the 2^52..2^53-1 range, so\n\t"
606 "@ the product is at most 106-bit long. Of the low 50 bits,\n\t"
607 "@ we only want to know if they are all zeros or not. Here,\n\t"
608 "@ we get the top 56 bits in r10:r11, and r8 will be non-zero\n\t"
609 "@ if and only if at least one of the low 50 bits is non-zero.\n\t"
610 "umull r8, r10, r4, r6 @ x0*y0\n\t"
611 "lsls r10, #7\n\t"
612 "orrs r10, r10, r8, lsr #25\n\t"
613 "eors r11, r11\n\t"
614 "umlal r10, r11, r4, r7 @ x0*y1\n\t"
615 "umlal r10, r11, r5, r6 @ x1*y0\n\t"
616 "orrs r8, r8, r10, lsl #7\n\t"
617 "lsrs r10, #25\n\t"
618 "orrs r10, r10, r11, lsl #7\n\t"
619 "eors r11, r11\n\t"
620 "umlal r10, r11, r5, r7 @ x1*y1\n\t"
621 "\n\t"
622 "@ Now r0, r2, r4, r5, r6 and r7 are free.\n\t"
623 "@ If any of the low 50 bits was non-zero, then we force the\n\t"
624 "@ low bit of r10 to 1.\n\t"
625 "rsbs r4, r8, #0\n\t"
626 "orrs r8, r8, r4\n\t"
627 "orrs r10, r10, r8, lsr #31\n\t"
628 "\n\t"
629 "@ r8 is free.\n\t"
630 "@ r10:r11 contains the product in the 2^54..2^56-1 range. We\n\t"
631 "@ normalize it to 2^54..2^55-1 (into r6:r7) with a conditional\n\t"
632 "@ shift (low bit is sticky). r5 contains -1 if the shift was done,\n\t"
633 "@ 0 otherwise.\n\t"
634 "ands r6, r10, #1\n\t"
635 "lsrs r5, r11, #23\n\t"
636 "rsbs r5, r5, #0\n\t"
637 "orrs r6, r6, r10, lsr #1\n\t"
638 "orrs r6, r6, r11, lsl #31\n\t"
639 "lsrs r7, r11, #1\n\t"
640 "eors r10, r10, r6\n\t"
641 "eors r11, r11, r7\n\t"
642 "bics r10, r10, r5\n\t"
643 "bics r11, r11, r5\n\t"
644 "eors r6, r6, r10\n\t"
645 "eors r7, r7, r11\n\t"
646 "\n\t"
647 "@ Compute aggregate exponent: ex + ey - 1023 + w\n\t"
648 "@ (where w = 1 if the conditional shift was done, 0 otherwise)\n\t"
649 "@ But we subtract 1 because the injection of the mantissa high\n\t"
650 "@ bit will increment the exponent by 1.\n\t"
651 "lsls r0, r1, #1\n\t"
652 "lsls r2, r3, #1\n\t"
653 "lsrs r0, #21\n\t"
654 "addw r4, r0, #0x7FF @ save ex + 2047 in r4\n\t"
655 "lsrs r2, #21\n\t"
656 "addw r8, r2, #0x7FF @ save ey + 2047 in r8\n\t"
657 "adds r2, r0\n\t"
658 "subw r2, r2, #1024\n\t"
659 "subs r2, r5\n\t"
660 "\n\t"
661 "@ r5 is free.\n\t"
662 "@ Also, if either of the source exponents is 0, or the result\n\t"
663 "@ exponent is 0 or negative, then the result is zero and the\n\t"
664 "@ mantissa and the exponent shall be clamped to zero. Since\n\t"
665 "@ r2 contains the result exponent minus 1, we test on r2\n\t"
666 "@ being strictly negative.\n\t"
667 "ands r4, r8 @ if bit 11 = 0 then one of the exponents was 0\n\t"
668 "mvns r5, r2\n\t"
669 "ands r5, r5, r4, lsl #20\n\t"
670 "ands r2, r2, r5, asr #31\n\t"
671 "ands r6, r6, r5, asr #31\n\t"
672 "ands r7, r7, r5, asr #31\n\t"
673 "\n\t"
674 "@ Sign is the XOR of the sign of the operands. This is true in\n\t"
675 "@ all cases, including very small results (exponent underflow)\n\t"
676 "@ and zeros.\n\t"
677 "eors r1, r3\n\t"
678 "bfc r1, #0, #31\n\t"
679 "\n\t"
680 "@ Plug in the exponent.\n\t"
681 "bfi r1, r2, #20, #11\n\t"
682 "\n\t"
683 "@ r2 and r3 are free.\n\t"
684 "@ Shift back to the normal 53-bit mantissa, with rounding.\n\t"
685 "@ Mantissa goes into r0:r1. For r1, we must use an addition\n\t"
686 "@ because the rounding may have triggered a carry, that should\n\t"
687 "@ be added to the exponent.\n\t"
688 "movs r4, r6\n\t"
689 "lsrs r0, r6, #2\n\t"
690 "orrs r0, r0, r7, lsl #30\n\t"
691 "adds r1, r1, r7, lsr #2\n\t"
692 "ands r4, #0x7\n\t"
693 "movs r3, #0xC8\n\t"
694 "lsrs r3, r4\n\t"
695 "ands r3, #1\n\t"
696 "adds r0, r3\n\t"
697 "adcs r1, #0\n\t"
698 "\n\t"
699 "pop { r4, r5, r6, r7, r8, r10, r11, pc }\n\t"
700 );
701 }
702
703 #else // yyyASM_CORTEXM4+0
704
705 fpr
706 fpr_mul(fpr x, fpr y)
707 {
708 uint64_t xu, yu, w, zu, zv;
709 uint32_t x0, x1, y0, y1, z0, z1, z2;
710 int ex, ey, d, e, s;
711
712 /*
713 * Extract absolute values as scaled unsigned integers. We
714 * don't extract exponents yet.
715 */
716 xu = (x & (((uint64_t)1 << 52) - 1)) | ((uint64_t)1 << 52);
717 yu = (y & (((uint64_t)1 << 52) - 1)) | ((uint64_t)1 << 52);
718
719 /*
720 * We have two 53-bit integers to multiply; we need to split
721 * each into a lower half and a upper half. Moreover, we
722 * prefer to have lower halves to be of 25 bits each, for
723 * reasons explained later on.
724 */
725 x0 = (uint32_t)xu & 0x01FFFFFF;
726 x1 = (uint32_t)(xu >> 25);
727 y0 = (uint32_t)yu & 0x01FFFFFF;
728 y1 = (uint32_t)(yu >> 25);
729 w = (uint64_t)x0 * (uint64_t)y0;
730 z0 = (uint32_t)w & 0x01FFFFFF;
731 z1 = (uint32_t)(w >> 25);
732 w = (uint64_t)x0 * (uint64_t)y1;
733 z1 += (uint32_t)w & 0x01FFFFFF;
734 z2 = (uint32_t)(w >> 25);
735 w = (uint64_t)x1 * (uint64_t)y0;
736 z1 += (uint32_t)w & 0x01FFFFFF;
737 z2 += (uint32_t)(w >> 25);
738 zu = (uint64_t)x1 * (uint64_t)y1;
739 z2 += (z1 >> 25);
740 z1 &= 0x01FFFFFF;
741 zu += z2;
742
743 /*
744 * Since xu and yu are both in the 2^52..2^53-1 range, the
745 * product is in the 2^104..2^106-1 range. We first reassemble
746 * it and round it into the 2^54..2^56-1 range; the bottom bit
747 * is made "sticky". Since the low limbs z0 and z1 are 25 bits
748 * each, we just take the upper part (zu), and consider z0 and
749 * z1 only for purposes of stickiness.
750 * (This is the reason why we chose 25-bit limbs above.)
751 */
752 zu |= ((z0 | z1) + 0x01FFFFFF) >> 25;
753
754 /*
755 * We normalize zu to the 2^54..s^55-1 range: it could be one
756 * bit too large at this point. This is done with a conditional
757 * right-shift that takes into account the sticky bit.
758 */
759 zv = (zu >> 1) | (zu & 1);
760 w = zu >> 55;
761 zu ^= (zu ^ zv) & -w;
762
763 /*
764 * Get the aggregate scaling factor:
765 *
766 * - Each exponent is biased by 1023.
767 *
768 * - Integral mantissas are scaled by 2^52, hence an
769 * extra 52 bias for each exponent.
770 *
771 * - However, we right-shifted z by 50 bits, and then
772 * by 0 or 1 extra bit (depending on the value of w).
773 *
774 * In total, we must add the exponents, then subtract
775 * 2 * (1023 + 52), then add 50 + w.
776 */
777 ex = (int)((x >> 52) & 0x7FF);
778 ey = (int)((y >> 52) & 0x7FF);
779 e = ex + ey - 2100 + (int)w;
780
781 /*
782 * Sign bit is the XOR of the operand sign bits.
783 */
784 s = (int)((x ^ y) >> 63);
785
786 /*
787 * Corrective actions for zeros: if either of the operands is
788 * zero, then the computations above were wrong. Test for zero
789 * is whether ex or ey is zero. We just have to set the mantissa
790 * (zu) to zero, the FPR() function will normalize e.
791 */
792 d = ((ex + 0x7FF) & (ey + 0x7FF)) >> 11;
793 zu &= -(uint64_t)d;
794
795 /*
796 * FPR() packs the result and applies proper rounding.
797 */
798 return FPR(s, e, zu);
799 }
800
801 #endif // yyyASM_CORTEXM4-
802
803 #if FALCON_ASM_CORTEXM4 // yyyASM_CORTEXM4+1
804
805 __attribute__((naked))
806 fpr
807 fpr_div(fpr x __attribute__((unused)), fpr y __attribute__((unused)))
808 {
809 __asm__ (
810 "push { r4, r5, r6, r7, r8, r10, r11, lr }\n\t"
811
812 "@ Extract mantissas of x and y, in r0:r4 and r2:r5, respectively.\n\t"
813 "@ We don't touch r1 and r3 as they contain the exponents and\n\t"
814 "@ signs, which we'll need later on.\n\t"
815 "ubfx r4, r1, #0, #20\n\t"
816 "ubfx r5, r3, #0, #20\n\t"
817 "orrs r4, r4, #0x00100000\n\t"
818 "orrs r5, r5, #0x00100000\n\t"
819 "\n\t"
820 "@ Perform bit-by-bit division. We want a 56-bit result in r8:r10\n\t"
821 "@ (low bit is 0). Bits come from the carry flag and are\n\t"
822 "@ injected with rrx, i.e. in position 31; we thus get bits in\n\t"
823 "@ the reverse order. Bits accumulate in r8; after the first 24\n\t"
824 "@ bits, we move the quotient bits to r10.\n\t"
825 "eors r8, r8\n\t"
826 "\n\t"
827
828 #define DIVSTEP \
829 "subs r6, r0, r2\n\t" \
830 "sbcs r7, r4, r5\n\t" \
831 "rrx r8, r8\n\t" \
832 "ands r6, r2, r8, asr #31\n\t" \
833 "ands r7, r5, r8, asr #31\n\t" \
834 "subs r0, r6\n\t" \
835 "sbcs r4, r7\n\t" \
836 "adds r0, r0, r0\n\t" \
837 "adcs r4, r4, r4\n\t"
838
839 #define DIVSTEP4 DIVSTEP DIVSTEP DIVSTEP DIVSTEP
840 #define DIVSTEP8 DIVSTEP4 DIVSTEP4
841
842 DIVSTEP8
843 DIVSTEP8
844 DIVSTEP8
845
846 "\n\t"
847 "@ We have the first 24 bits of the quotient, move them to r10.\n\t"
848 "rbit r10, r8\n\t"
849 "\n\t"
850
851 DIVSTEP8
852 DIVSTEP8
853 DIVSTEP8
854 DIVSTEP4 DIVSTEP DIVSTEP DIVSTEP
855
856 #undef DIVSTEP
857 #undef DIVSTEP4
858 #undef DIVSTEP8
859
860 "\n\t"
861 "@ Lowest bit will be set if remainder is non-zero at this point\n\t"
862 "@ (this is the 'sticky' bit).\n\t"
863 "subs r0, #1\n\t"
864 "sbcs r4, #0\n\t"
865 "rrx r8, r8\n\t"
866 "\n\t"
867 "@ We now have the next (low) 32 bits of the quotient.\n\t"
868 "rbit r8, r8\n\t"
869 "\n\t"
870 "@ Since both operands had their top bit set, we know that the\n\t"
871 "@ result at this point is in 2^54..2^56-1. We scale it down\n\t"
872 "@ to 2^54..2^55-1 with a conditional shift. We also write the\n\t"
873 "@ result in r4:r5. If the shift is done, r6 will contain -1.\n\t"
874 "ands r4, r8, #1\n\t"
875 "lsrs r6, r10, #23\n\t"
876 "rsbs r6, r6, #0\n\t"
877 "orrs r4, r4, r8, lsr #1\n\t"
878 "orrs r4, r4, r10, lsl #31\n\t"
879 "lsrs r5, r10, #1\n\t"
880 "eors r8, r8, r4\n\t"
881 "eors r10, r10, r5\n\t"
882 "bics r8, r8, r6\n\t"
883 "bics r10, r10, r6\n\t"
884 "eors r4, r4, r8\n\t"
885 "eors r5, r5, r10\n\t"
886 "\n\t"
887 "@ Compute aggregate exponent: ex - ey + 1022 + w\n\t"
888 "@ (where w = 1 if the conditional shift was done, 0 otherwise)\n\t"
889 "@ But we subtract 1 because the injection of the mantissa high\n\t"
890 "@ bit will increment the exponent by 1.\n\t"
891 "lsls r0, r1, #1\n\t"
892 "lsls r2, r3, #1\n\t"
893 "lsrs r0, r0, #21\n\t"
894 "addw r7, r0, #0x7FF @ save ex + 2047 in r7\n\t"
895 "subs r0, r0, r2, lsr #21\n\t"
896 "addw r0, r0, #1021\n\t"
897 "subs r0, r6\n\t"
898 "\n\t"
899 "@ If the x operand was zero, then the computation was wrong and\n\t"
900 "@ the result is zero. Also, if the result exponent is zero or\n\t"
901 "@ negative, then the mantissa shall be clamped to zero. Since r0\n\t"
902 "@ contains the result exponent minus 1, we test on r0 being\n\t"
903 "@ strictly negative.\n\t"
904 "mvns r2, r0\n\t"
905 "ands r2, r2, r7, lsl #20\n\t"
906 "ands r0, r0, r2, asr #31\n\t"
907 "ands r4, r4, r2, asr #31\n\t"
908 "ands r5, r5, r2, asr #31\n\t"
909 "\n\t"
910 "@ Sign is the XOR of the sign of the operands. This is true in\n\t"
911 "@ all cases, including very small results (exponent underflow)\n\t"
912 "@ and zeros.\n\t"
913 "eors r1, r3\n\t"
914 "bfc r1, #0, #31\n\t"
915 "\n\t"
916 "@ Plug in the exponent.\n\t"
917 "bfi r1, r0, #20, #11\n\t"
918 "\n\t"
919 "@ Shift back to the normal 53-bit mantissa, with rounding.\n\t"
920 "@ Mantissa goes into r0:r1. For r1, we must use an addition\n\t"
921 "@ because the rounding may have triggered a carry, that should\n\t"
922 "@ be added to the exponent.\n\t"
923 "movs r6, r4\n\t"
924 "lsrs r0, r4, #2\n\t"
925 "orrs r0, r0, r5, lsl #30\n\t"
926 "adds r1, r1, r5, lsr #2\n\t"
927 "ands r6, #0x7\n\t"
928 "movs r3, #0xC8\n\t"
929 "lsrs r3, r6\n\t"
930 "ands r3, #1\n\t"
931 "adds r0, r3\n\t"
932 "adcs r1, #0\n\t"
933 "\n\t"
934 "pop { r4, r5, r6, r7, r8, r10, r11, pc }\n\t"
935 );
936 }
937
938 #else // yyyASM_CORTEXM4+0
939
940 fpr
941 fpr_div(fpr x, fpr y)
942 {
943 uint64_t xu, yu, q, q2, w;
944 int i, ex, ey, e, d, s;
945
946 /*
947 * Extract mantissas of x and y (unsigned).
948 */
949 xu = (x & (((uint64_t)1 << 52) - 1)) | ((uint64_t)1 << 52);
950 yu = (y & (((uint64_t)1 << 52) - 1)) | ((uint64_t)1 << 52);
951
952 /*
953 * Perform bit-by-bit division of xu by yu. We run it for 55 bits.
954 */
955 q = 0;
956 for (i = 0; i < 55; i ++) {
957 /*
958 * If yu is less than or equal xu, then subtract it and
959 * push a 1 in the quotient; otherwise, leave xu unchanged
960 * and push a 0.
961 */
962 uint64_t b;
963
964 b = ((xu - yu) >> 63) - 1;
965 xu -= b & yu;
966 q |= b & 1;
967 xu <<= 1;
968 q <<= 1;
969 }
970
971 /*
972 * We got 55 bits in the quotient, followed by an extra zero. We
973 * want that 56th bit to be "sticky": it should be a 1 if and
974 * only if the remainder (xu) is non-zero.
975 */
976 q |= (xu | -xu) >> 63;
977
978 /*
979 * Quotient is at most 2^56-1. Its top bit may be zero, but in
980 * that case the next-to-top bit will be a one, since the
981 * initial xu and yu were both in the 2^52..2^53-1 range.
982 * We perform a conditional shift to normalize q to the
983 * 2^54..2^55-1 range (with the bottom bit being sticky).
984 */
985 q2 = (q >> 1) | (q & 1);
986 w = q >> 55;
987 q ^= (q ^ q2) & -w;
988
989 /*
990 * Extract exponents to compute the scaling factor:
991 *
992 * - Each exponent is biased and we scaled them up by
993 * 52 bits; but these biases will cancel out.
994 *
995 * - The division loop produced a 55-bit shifted result,
996 * so we must scale it down by 55 bits.
997 *
998 * - If w = 1, we right-shifted the integer by 1 bit,
999 * hence we must add 1 to the scaling.
1000 */
1001 ex = (int)((x >> 52) & 0x7FF);
1002 ey = (int)((y >> 52) & 0x7FF);
1003 e = ex - ey - 55 + (int)w;
1004
1005 /*
1006 * Sign is the XOR of the signs of the operands.
1007 */
1008 s = (int)((x ^ y) >> 63);
1009
1010 /*
1011 * Corrective actions for zeros: if x = 0, then the computation
1012 * is wrong, and we must clamp e and q to 0. We do not care
1013 * about the case y = 0 (as per assumptions in this module,
1014 * the caller does not perform divisions by zero).
1015 */
1016 d = (ex + 0x7FF) >> 11;
1017 s &= d;
1018 e &= -d;
1019 q &= -(uint64_t)d;
1020
1021 /*
1022 * FPR() packs the result and applies proper rounding.
1023 */
1024 return FPR(s, e, q);
1025 }
1026
1027 #endif // yyyASM_CORTEXM4-
1028
1029 #if FALCON_ASM_CORTEXM4 // yyyASM_CORTEXM4+1
1030
1031 __attribute__((naked))
1032 fpr
1033 fpr_sqrt(fpr x __attribute__((unused)))
1034 {
1035 __asm__ (
1036 "push { r4, r5, r6, r7, r8, r10, r11, lr }\n\t"
1037 "\n\t"
1038 "@ Extract mantissa (r0:r1) and exponent (r2). We assume that the\n\t"
1039 "@ sign is positive. If the source is zero, then the mantissa is\n\t"
1040 "@ set to 0.\n\t"
1041 "lsrs r2, r1, #20\n\t"
1042 "bfc r1, #20, #12\n\t"
1043 "addw r3, r2, #0x7FF\n\t"
1044 "subw r2, r2, #1023\n\t"
1045 "lsrs r3, r3, #11\n\t"
1046 "orrs r1, r1, r3, lsl #20\n\t"
1047 "\n\t"
1048 "@ If the exponent is odd, then multiply mantissa by 2 and subtract\n\t"
1049 "@ 1 from the exponent.\n\t"
1050 "ands r3, r2, #1\n\t"
1051 "subs r2, r2, r3\n\t"
1052 "rsbs r3, r3, #0\n\t"
1053 "ands r4, r1, r3\n\t"
1054 "ands r3, r0\n\t"
1055 "adds r0, r3\n\t"
1056 "adcs r1, r4\n\t"
1057 "\n\t"
1058 "@ Left-shift the mantissa by 9 bits to put it in the\n\t"
1059 "@ 2^61..2^63-1 range (unless it is exactly 0).\n\t"
1060 "lsls r1, r1, #9\n\t"
1061 "orrs r1, r1, r0, lsr #23\n\t"
1062 "lsls r0, r0, #9\n\t"
1063 "\n\t"
1064 "@ Compute the square root bit-by-bit.\n\t"
1065 "@ There are 54 iterations; first 30 can work on top word only.\n\t"
1066 "@ q = r3 (bit-reversed)\n\t"
1067 "@ s = r5\n\t"
1068 "eors r3, r3\n\t"
1069 "eors r5, r5\n\t"
1070
1071 #define SQRT_STEP_HI(bit) \
1072 "orrs r6, r5, #(1 << (" #bit "))\n\t" \
1073 "subs r7, r1, r6\n\t" \
1074 "rrx r3, r3\n\t" \
1075 "ands r6, r6, r3, asr #31\n\t" \
1076 "subs r1, r1, r6\n\t" \
1077 "lsrs r6, r3, #31\n\t" \
1078 "orrs r5, r5, r6, lsl #((" #bit ") + 1)\n\t" \
1079 "adds r0, r0\n\t" \
1080 "adcs r1, r1\n\t"
1081
1082 #define SQRT_STEP_HIx5(b) \
1083 SQRT_STEP_HI((b)+4) \
1084 SQRT_STEP_HI((b)+3) \
1085 SQRT_STEP_HI((b)+2) \
1086 SQRT_STEP_HI((b)+1) \
1087 SQRT_STEP_HI(b)
1088
1089 SQRT_STEP_HIx5(25)
1090 SQRT_STEP_HIx5(20)
1091 SQRT_STEP_HIx5(15)
1092 SQRT_STEP_HIx5(10)
1093 SQRT_STEP_HIx5(5)
1094 SQRT_STEP_HIx5(0)
1095
1096 #undef SQRT_STEP_HI
1097 #undef SQRT_STEP_HIx5
1098
1099 "@ Top 30 bits of the result must be reversed: they were\n\t"
1100 "@ accumulated with rrx (hence from the top bit).\n\t"
1101 "rbit r3, r3\n\t"
1102 "\n\t"
1103 "@ For the next 24 iterations, we must use two-word operations.\n\t"
1104 "@ bits of q now accumulate in r4\n\t"
1105 "@ s is in r6:r5\n\t"
1106 "eors r4, r4\n\t"
1107 "eors r6, r6\n\t"
1108 "\n\t"
1109 "@ First iteration is special because the potential bit goes into\n\t"
1110 "@ r5, not r6.\n\t"
1111 "orrs r7, r6, #(1 << 31)\n\t"
1112 "subs r8, r0, r7\n\t"
1113 "sbcs r10, r1, r5\n\t"
1114 "rrx r4, r4\n\t"
1115 "ands r7, r7, r4, asr #31\n\t"
1116 "ands r8, r5, r4, asr #31\n\t"
1117 "subs r0, r0, r7\n\t"
1118 "sbcs r1, r1, r8\n\t"
1119 "lsrs r7, r4, #31\n\t"
1120 "orrs r5, r5, r4, lsr #31\n\t"
1121 "adds r0, r0\n\t"
1122 "adcs r1, r1\n\t"
1123
1124 #define SQRT_STEP_LO(bit) \
1125 "orrs r7, r6, #(1 << (" #bit "))\n\t" \
1126 "subs r8, r0, r7\n\t" \
1127 "sbcs r10, r1, r5\n\t" \
1128 "rrx r4, r4\n\t" \
1129 "ands r7, r7, r4, asr #31\n\t" \
1130 "ands r8, r5, r4, asr #31\n\t" \
1131 "subs r0, r0, r7\n\t" \
1132 "sbcs r1, r1, r8\n\t" \
1133 "lsrs r7, r4, #31\n\t" \
1134 "orrs r6, r6, r7, lsl #((" #bit ") + 1)\n\t" \
1135 "adds r0, r0\n\t" \
1136 "adcs r1, r1\n\t"
1137
1138 #define SQRT_STEP_LOx4(b) \
1139 SQRT_STEP_LO((b)+3) \
1140 SQRT_STEP_LO((b)+2) \
1141 SQRT_STEP_LO((b)+1) \
1142 SQRT_STEP_LO(b)
1143
1144 SQRT_STEP_LO(30)
1145 SQRT_STEP_LO(29)
1146 SQRT_STEP_LO(28)
1147 SQRT_STEP_LOx4(24)
1148 SQRT_STEP_LOx4(20)
1149 SQRT_STEP_LOx4(16)
1150 SQRT_STEP_LOx4(12)
1151 SQRT_STEP_LOx4(8)
1152
1153 #undef SQRT_STEP_LO
1154 #undef SQRT_STEP_LOx4
1155
1156 "@ Put low 24 bits in the right order.\n\t"
1157 "rbit r4, r4\n\t"
1158 "\n\t"
1159 "@ We have a 54-bit result; compute the 55-th bit as the 'sticky'\n\t"
1160 "@ bit: it is non-zero if and only if r0:r1 is non-zero. We put the\n\t"
1161 "@ three low bits (including the sticky bit) in r5.\n\t"
1162 "orrs r0, r1\n\t"
1163 "rsbs r1, r0, #0\n\t"
1164 "orrs r0, r1\n\t"
1165 "lsls r5, r4, #1\n\t"
1166 "orrs r5, r5, r0, lsr #31\n\t"
1167 "ands r5, #0x7\n\t"
1168 "\n\t"
1169 "@ Compute the rounding: r6 is set to 0 or 1, and will be added\n\t"
1170 "@ to the mantissa.\n\t"
1171 "movs r6, #0xC8\n\t"
1172 "lsrs r6, r5\n\t"
1173 "ands r6, #1\n\t"
1174 "\n\t"
1175 "@ Put the mantissa (53 bits, in the 2^52..2^53-1 range) in r0:r1\n\t"
1176 "@ (rounding not applied yet).\n\t"
1177 "lsrs r0, r4, #1\n\t"
1178 "orrs r0, r0, r3, lsl #23\n\t"
1179 "lsrs r1, r3, #9\n\t"
1180 "\n\t"
1181 "@ Compute new exponent. This is half the old one (then reencoded\n\t"
1182 "@ by adding 1023). Exception: if the mantissa is zero, then the\n\t"
1183 "@ encoded exponent is set to 0. At that point, if the mantissa\n\t"
1184 "@ is non-zero, then its high bit (bit 52, i.e. bit 20 of r1) is\n\t"
1185 "@ non-zero. Note that the exponent cannot go out of range.\n\t"
1186 "lsrs r2, r2, #1\n\t"
1187 "addw r2, r2, #1023\n\t"
1188 "lsrs r5, r1, #20\n\t"
1189 "rsbs r5, r5, #0\n\t"
1190 "ands r2, r5\n\t"
1191 "\n\t"
1192 "@ Place exponent. This overwrites the high bit of the mantissa.\n\t"
1193 "bfi r1, r2, #20, #11\n\t"
1194 "\n\t"
1195 "@ Apply rounding. This may create a carry that will spill into\n\t"
1196 "@ the exponent, which is exactly what should be done in that case\n\t"
1197 "@ (i.e. increment the exponent).\n\t"
1198 "adds r0, r0, r6\n\t"
1199 "adcs r1, r1, #0\n\t"
1200 "\n\t"
1201 "pop { r4, r5, r6, r7, r8, r10, r11, pc }\n\t"
1202 );
1203 }
1204
1205 #else // yyyASM_CORTEXM4+0
1206
1207 fpr
1208 fpr_sqrt(fpr x)
1209 {
1210 uint64_t xu, q, s, r;
1211 int ex, e;
1212
1213 /*
1214 * Extract the mantissa and the exponent. We don't care about
1215 * the sign: by assumption, the operand is nonnegative.
1216 * We want the "true" exponent corresponding to a mantissa
1217 * in the 1..2 range.
1218 */
1219 xu = (x & (((uint64_t)1 << 52) - 1)) | ((uint64_t)1 << 52);
1220 ex = (int)((x >> 52) & 0x7FF);
1221 e = ex - 1023;
1222
1223 /*
1224 * If the exponent is odd, double the mantissa and decrement
1225 * the exponent. The exponent is then halved to account for
1226 * the square root.
1227 */
1228 xu += xu & -(uint64_t)(e & 1);
1229 e >>= 1;
1230
1231 /*
1232 * Double the mantissa.
1233 */
1234 xu <<= 1;
1235
1236 /*
1237 * We now have a mantissa in the 2^53..2^55-1 range. It
1238 * represents a value between 1 (inclusive) and 4 (exclusive)
1239 * in fixed point notation (with 53 fractional bits). We
1240 * compute the square root bit by bit.
1241 */
1242 q = 0;
1243 s = 0;
1244 r = (uint64_t)1 << 53;
1245 for (int i = 0; i < 54; i ++) {
1246 uint64_t t, b;
1247
1248 t = s + r;
1249 b = ((xu - t) >> 63) - 1;
1250 s += (r << 1) & b;
1251 xu -= t & b;
1252 q += r & b;
1253 xu <<= 1;
1254 r >>= 1;
1255 }
1256
1257 /*
1258 * Now, q is a rounded-low 54-bit value, with a leading 1,
1259 * 52 fractional digits, and an additional guard bit. We add
1260 * an extra sticky bit to account for what remains of the operand.
1261 */
1262 q <<= 1;
1263 q |= (xu | -xu) >> 63;
1264
1265 /*
1266 * Result q is in the 2^54..2^55-1 range; we bias the exponent
1267 * by 54 bits (the value e at that point contains the "true"
1268 * exponent, but q is now considered an integer, i.e. scaled
1269 * up.
1270 */
1271 e -= 54;
1272
1273 /*
1274 * Corrective action for an operand of value zero.
1275 */
1276 q &= -(uint64_t)((ex + 0x7FF) >> 11);
1277
1278 /*
1279 * Apply rounding and back result.
1280 */
1281 return FPR(0, e, q);
1282 }
1283
1284 #endif // yyyASM_CORTEXM4-
1285
1286 uint64_t
1287 fpr_expm_p63(fpr x, fpr ccs)
1288 {
1289 /*
1290 * Polynomial approximation of exp(-x) is taken from FACCT:
1291 * https://eprint.iacr.org/2018/1234
1292 * Specifically, values are extracted from the implementation
1293 * referenced from the FACCT article, and available at:
1294 * https://github.com/raykzhao/gaussian
1295 * Here, the coefficients have been scaled up by 2^63 and
1296 * converted to integers.
1297 *
1298 * Tests over more than 24 billions of random inputs in the
1299 * 0..log(2) range have never shown a deviation larger than
1300 * 2^(-50) from the true mathematical value.
1301 */
1302 static const uint64_t C[] = {
1303 0x00000004741183A3u,
1304 0x00000036548CFC06u,
1305 0x0000024FDCBF140Au,
1306 0x0000171D939DE045u,
1307 0x0000D00CF58F6F84u,
1308 0x000680681CF796E3u,
1309 0x002D82D8305B0FEAu,
1310 0x011111110E066FD0u,
1311 0x0555555555070F00u,
1312 0x155555555581FF00u,
1313 0x400000000002B400u,
1314 0x7FFFFFFFFFFF4800u,
1315 0x8000000000000000u
1316 };
1317
1318 uint64_t z, y;
1319 unsigned u;
1320 uint32_t z0, z1, y0, y1;
1321 uint64_t a, b;
1322
1323 y = C[0];
1324 z = (uint64_t)fpr_trunc(fpr_mul(x, fpr_ptwo63)) << 1;
1325 for (u = 1; u < (sizeof C) / sizeof(C[0]); u ++) {
1326 /*
1327 * Compute product z * y over 128 bits, but keep only
1328 * the top 64 bits.
1329 *
1330 * TODO: On some architectures/compilers we could use
1331 * some intrinsics (__umulh() on MSVC) or other compiler
1332 * extensions (unsigned __int128 on GCC / Clang) for
1333 * improved speed; however, most 64-bit architectures
1334 * also have appropriate IEEE754 floating-point support,
1335 * which is better.
1336 */
1337 uint64_t c;
1338
1339 z0 = (uint32_t)z;
1340 z1 = (uint32_t)(z >> 32);
1341 y0 = (uint32_t)y;
1342 y1 = (uint32_t)(y >> 32);
1343 a = ((uint64_t)z0 * (uint64_t)y1)
1344 + (((uint64_t)z0 * (uint64_t)y0) >> 32);
1345 b = ((uint64_t)z1 * (uint64_t)y0);
1346 c = (a >> 32) + (b >> 32);
1347 c += (((uint64_t)(uint32_t)a + (uint64_t)(uint32_t)b) >> 32);
1348 c += (uint64_t)z1 * (uint64_t)y1;
1349 y = C[u] - c;
1350 }
1351
1352 /*
1353 * The scaling factor must be applied at the end. Since y is now
1354 * in fixed-point notation, we have to convert the factor to the
1355 * same format, and do an extra integer multiplication.
1356 */
1357 z = (uint64_t)fpr_trunc(fpr_mul(ccs, fpr_ptwo63)) << 1;
1358 z0 = (uint32_t)z;
1359 z1 = (uint32_t)(z >> 32);
1360 y0 = (uint32_t)y;
1361 y1 = (uint32_t)(y >> 32);
1362 a = ((uint64_t)z0 * (uint64_t)y1)
1363 + (((uint64_t)z0 * (uint64_t)y0) >> 32);
1364 b = ((uint64_t)z1 * (uint64_t)y0);
1365 y = (a >> 32) + (b >> 32);
1366 y += (((uint64_t)(uint32_t)a + (uint64_t)(uint32_t)b) >> 32);
1367 y += (uint64_t)z1 * (uint64_t)y1;
1368
1369 return y;
1370 }
1371
1372 const fpr fpr_gm_tab[] = {
1373 0, 0,
1374 9223372036854775808U, 4607182418800017408U,
1375 4604544271217802189U, 4604544271217802189U,
1376 13827916308072577997U, 4604544271217802189U,
1377 4606496786581982534U, 4600565431771507043U,
1378 13823937468626282851U, 4606496786581982534U,
1379 4600565431771507043U, 4606496786581982534U,
1380 13829868823436758342U, 4600565431771507043U,
1381 4607009347991985328U, 4596196889902818827U,
1382 13819568926757594635U, 4607009347991985328U,
1383 4603179351334086856U, 4605664432017547683U,
1384 13829036468872323491U, 4603179351334086856U,
1385 4605664432017547683U, 4603179351334086856U,
1386 13826551388188862664U, 4605664432017547683U,
1387 4596196889902818827U, 4607009347991985328U,
1388 13830381384846761136U, 4596196889902818827U,
1389 4607139046673687846U, 4591727299969791020U,
1390 13815099336824566828U, 4607139046673687846U,
1391 4603889326261607894U, 4605137878724712257U,
1392 13828509915579488065U, 4603889326261607894U,
1393 4606118860100255153U, 4602163548591158843U,
1394 13825535585445934651U, 4606118860100255153U,
1395 4598900923775164166U, 4606794571824115162U,
1396 13830166608678890970U, 4598900923775164166U,
1397 4606794571824115162U, 4598900923775164166U,
1398 13822272960629939974U, 4606794571824115162U,
1399 4602163548591158843U, 4606118860100255153U,
1400 13829490896955030961U, 4602163548591158843U,
1401 4605137878724712257U, 4603889326261607894U,
1402 13827261363116383702U, 4605137878724712257U,
1403 4591727299969791020U, 4607139046673687846U,
1404 13830511083528463654U, 4591727299969791020U,
1405 4607171569234046334U, 4587232218149935124U,
1406 13810604255004710932U, 4607171569234046334U,
1407 4604224084862889120U, 4604849113969373103U,
1408 13828221150824148911U, 4604224084862889120U,
1409 4606317631232591731U, 4601373767755717824U,
1410 13824745804610493632U, 4606317631232591731U,
1411 4599740487990714333U, 4606655894547498725U,
1412 13830027931402274533U, 4599740487990714333U,
1413 4606912484326125783U, 4597922303871901467U,
1414 13821294340726677275U, 4606912484326125783U,
1415 4602805845399633902U, 4605900952042040894U,
1416 13829272988896816702U, 4602805845399633902U,
1417 4605409869824231233U, 4603540801876750389U,
1418 13826912838731526197U, 4605409869824231233U,
1419 4594454542771183930U, 4607084929468638487U,
1420 13830456966323414295U, 4594454542771183930U,
1421 4607084929468638487U, 4594454542771183930U,
1422 13817826579625959738U, 4607084929468638487U,
1423 4603540801876750389U, 4605409869824231233U,
1424 13828781906679007041U, 4603540801876750389U,
1425 4605900952042040894U, 4602805845399633902U,
1426 13826177882254409710U, 4605900952042040894U,
1427 4597922303871901467U, 4606912484326125783U,
1428 13830284521180901591U, 4597922303871901467U,
1429 4606655894547498725U, 4599740487990714333U,
1430 13823112524845490141U, 4606655894547498725U,
1431 4601373767755717824U, 4606317631232591731U,
1432 13829689668087367539U, 4601373767755717824U,
1433 4604849113969373103U, 4604224084862889120U,
1434 13827596121717664928U, 4604849113969373103U,
1435 4587232218149935124U, 4607171569234046334U,
1436 13830543606088822142U, 4587232218149935124U,
1437 4607179706000002317U, 4582730748936808062U,
1438 13806102785791583870U, 4607179706000002317U,
1439 4604386048625945823U, 4604698657331085206U,
1440 13828070694185861014U, 4604386048625945823U,
1441 4606409688975526202U, 4600971798440897930U,
1442 13824343835295673738U, 4606409688975526202U,
1443 4600154912527631775U, 4606578871587619388U,
1444 13829950908442395196U, 4600154912527631775U,
1445 4606963563043808649U, 4597061974398750563U,
1446 13820434011253526371U, 4606963563043808649U,
1447 4602994049708411683U, 4605784983948558848U,
1448 13829157020803334656U, 4602994049708411683U,
1449 4605539368864982914U, 4603361638657888991U,
1450 13826733675512664799U, 4605539368864982914U,
1451 4595327571478659014U, 4607049811591515049U,
1452 13830421848446290857U, 4595327571478659014U,
1453 4607114680469659603U, 4593485039402578702U,
1454 13816857076257354510U, 4607114680469659603U,
1455 4603716733069447353U, 4605276012900672507U,
1456 13828648049755448315U, 4603716733069447353U,
1457 4606012266443150634U, 4602550884377336506U,
1458 13825922921232112314U, 4606012266443150634U,
1459 4598476289818621559U, 4606856142606846307U,
1460 13830228179461622115U, 4598476289818621559U,
1461 4606727809065869586U, 4599322407794599425U,
1462 13822694444649375233U, 4606727809065869586U,
1463 4601771097584682078U, 4606220668805321205U,
1464 13829592705660097013U, 4601771097584682078U,
1465 4604995550503212910U, 4604058477489546729U,
1466 13827430514344322537U, 4604995550503212910U,
1467 4589965306122607094U, 4607158013403433018U,
1468 13830530050258208826U, 4589965306122607094U,
1469 4607158013403433018U, 4589965306122607094U,
1470 13813337342977382902U, 4607158013403433018U,
1471 4604058477489546729U, 4604995550503212910U,
1472 13828367587357988718U, 4604058477489546729U,
1473 4606220668805321205U, 4601771097584682078U,
1474 13825143134439457886U, 4606220668805321205U,
1475 4599322407794599425U, 4606727809065869586U,
1476 13830099845920645394U, 4599322407794599425U,
1477 4606856142606846307U, 4598476289818621559U,
1478 13821848326673397367U, 4606856142606846307U,
1479 4602550884377336506U, 4606012266443150634U,
1480 13829384303297926442U, 4602550884377336506U,
1481 4605276012900672507U, 4603716733069447353U,
1482 13827088769924223161U, 4605276012900672507U,
1483 4593485039402578702U, 4607114680469659603U,
1484 13830486717324435411U, 4593485039402578702U,
1485 4607049811591515049U, 4595327571478659014U,
1486 13818699608333434822U, 4607049811591515049U,
1487 4603361638657888991U, 4605539368864982914U,
1488 13828911405719758722U, 4603361638657888991U,
1489 4605784983948558848U, 4602994049708411683U,
1490 13826366086563187491U, 4605784983948558848U,
1491 4597061974398750563U, 4606963563043808649U,
1492 13830335599898584457U, 4597061974398750563U,
1493 4606578871587619388U, 4600154912527631775U,
1494 13823526949382407583U, 4606578871587619388U,
1495 4600971798440897930U, 4606409688975526202U,
1496 13829781725830302010U, 4600971798440897930U,
1497 4604698657331085206U, 4604386048625945823U,
1498 13827758085480721631U, 4604698657331085206U,
1499 4582730748936808062U, 4607179706000002317U,
1500 13830551742854778125U, 4582730748936808062U,
1501 4607181740574479067U, 4578227681973159812U,
1502 13801599718827935620U, 4607181740574479067U,
1503 4604465633578481725U, 4604621949701367983U,
1504 13827993986556143791U, 4604465633578481725U,
1505 4606453861145241227U, 4600769149537129431U,
1506 13824141186391905239U, 4606453861145241227U,
1507 4600360675823176935U, 4606538458821337243U,
1508 13829910495676113051U, 4600360675823176935U,
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1843 4598136582470364665U, 4606898891031025132U,
1844 13830270927885800940U, 4598136582470364665U,
1845 4606674353838411301U, 4599636300858866724U,
1846 13823008337713642532U, 4606674353838411301U,
1847 4601473544562720001U, 4606293848208650998U,
1848 13829665885063426806U, 4601473544562720001U,
1849 4604886103475043762U, 4604183020748362039U,
1850 13827555057603137847U, 4604886103475043762U,
1851 4588115294056142819U, 4607168688050493276U,
1852 13830540724905269084U, 4588115294056142819U,
1853 4607144295058764886U, 4591287158938884897U,
1854 13814659195793660705U, 4607144295058764886U,
1855 4603931940768740167U, 4605102686554936490U,
1856 13828474723409712298U, 4603931940768740167U,
1857 4606144763310860551U, 4602065906208722008U,
1858 13825437943063497816U, 4606144763310860551U,
1859 4599006600037663623U, 4606778366364612594U,
1860 13830150403219388402U, 4599006600037663623U,
1861 4606810452769876110U, 4598795050632330097U,
1862 13822167087487105905U, 4606810452769876110U,
1863 4602260871257280788U, 4606092657816072624U,
1864 13829464694670848432U, 4602260871257280788U,
1865 4605172808754305228U, 4603846496621587377U,
1866 13827218533476363185U, 4605172808754305228U,
1867 4592167175087283203U, 4607133460805585796U,
1868 13830505497660361604U, 4592167175087283203U,
1869 4607019963775302583U, 4595979936813835462U,
1870 13819351973668611270U, 4607019963775302583U,
1871 4603225210076562971U, 4605633586259814045U,
1872 13829005623114589853U, 4603225210076562971U,
1873 4605694995810664660U, 4603133304188877240U,
1874 13826505341043653048U, 4605694995810664660U,
1875 4596413578358834022U, 4606998399608725124U,
1876 13830370436463500932U, 4596413578358834022U,
1877 4606517779747998088U, 4600463181646572228U,
1878 13823835218501348036U, 4606517779747998088U,
1879 4600667422348321968U, 4606475480113671417U,
1880 13829847516968447225U, 4600667422348321968U,
1881 4604583231088591477U, 4604505071555817232U,
1882 13827877108410593040U, 4604583231088591477U,
1883 4573724215515480177U, 4607182249242036882U,
1884 13830554286096812690U, 4573724215515480177U,
1885 4607182376410422530U, 4569220649180767418U,
1886 13792592686035543226U, 4607182376410422530U,
1887 4604524701268679793U, 4604563781218984604U,
1888 13827935818073760412U, 4604524701268679793U,
1889 4606486172460753999U, 4600616459743653188U,
1890 13823988496598428996U, 4606486172460753999U,
1891 4600514338912178239U, 4606507322377452870U,
1892 13829879359232228678U, 4600514338912178239U,
1893 4607003915349878877U, 4596305267720071930U,
1894 13819677304574847738U, 4607003915349878877U,
1895 4603156351203636159U, 4605679749231851918U,
1896 13829051786086627726U, 4603156351203636159U,
1897 4605649044311923410U, 4603202304363743346U,
1898 13826574341218519154U, 4605649044311923410U,
1899 4596088445927168004U, 4607014697483910382U,
1900 13830386734338686190U, 4596088445927168004U,
1901 4607136295912168606U, 4591947271803021404U,
1902 13815319308657797212U, 4607136295912168606U,
1903 4603867938232615808U, 4605155376589456981U,
1904 13828527413444232789U, 4603867938232615808U,
1905 4606105796280968177U, 4602212250118051877U,
1906 13825584286972827685U, 4606105796280968177U,
1907 4598848011564831930U, 4606802552898869248U,
1908 13830174589753645056U, 4598848011564831930U,
1909 4606786509620734768U, 4598953786765296928U,
1910 13822325823620072736U, 4606786509620734768U,
1911 4602114767134999006U, 4606131849150971908U,
1912 13829503886005747716U, 4602114767134999006U,
1913 4605120315324767624U, 4603910660507251362U,
1914 13827282697362027170U, 4605120315324767624U,
1915 4591507261658050721U, 4607141713064252300U,
1916 13830513749919028108U, 4591507261658050721U,
1917 4607170170974224083U, 4587673791460508439U,
1918 13811045828315284247U, 4607170170974224083U,
1919 4604203581176243359U, 4604867640218014515U,
1920 13828239677072790323U, 4604203581176243359U,
1921 4606305777984577632U, 4601423692641949331U,
1922 13824795729496725139U, 4606305777984577632U,
1923 4599688422741010356U, 4606665164148251002U,
1924 13830037201003026810U, 4599688422741010356U,
1925 4606905728766014348U, 4598029484874872834U,
1926 13821401521729648642U, 4606905728766014348U,
1927 4602782121393764535U, 4605915122243179241U,
1928 13829287159097955049U, 4602782121393764535U,
1929 4605393374401988274U, 4603562972219549215U,
1930 13826935009074325023U, 4605393374401988274U,
1931 4594345179472540681U, 4607088942243446236U,
1932 13830460979098222044U, 4594345179472540681U,
1933 4607080832832247697U, 4594563856311064231U,
1934 13817935893165840039U, 4607080832832247697U,
1935 4603518581031047189U, 4605426297151190466U,
1936 13828798334005966274U, 4603518581031047189U,
1937 4605886709123365959U, 4602829525820289164U,
1938 13826201562675064972U, 4605886709123365959U,
1939 4597815040470278984U, 4606919157647773535U,
1940 13830291194502549343U, 4597815040470278984U,
1941 4606646545123403481U, 4599792496117920694U,
1942 13823164532972696502U, 4606646545123403481U,
1943 4601323770373937522U, 4606329407841126011U,
1944 13829701444695901819U, 4601323770373937522U,
1945 4604830524903495634U, 4604244531615310815U,
1946 13827616568470086623U, 4604830524903495634U,
1947 4586790578280679046U, 4607172882816799076U,
1948 13830544919671574884U, 4586790578280679046U,
1949 4607178985458280057U, 4583614727651146525U,
1950 13806986764505922333U, 4607178985458280057U,
1951 4604366005771528720U, 4604717681185626434U,
1952 13828089718040402242U, 4604366005771528720U,
1953 4606398451906509788U, 4601022290077223616U,
1954 13824394326931999424U, 4606398451906509788U,
1955 4600103317933788342U, 4606588777269136769U,
1956 13829960814123912577U, 4600103317933788342U,
1957 4606957467106717424U, 4597169786279785693U,
1958 13820541823134561501U, 4606957467106717424U,
1959 4602970680601913687U, 4605799732098147061U,
1960 13829171768952922869U, 4602970680601913687U,
1961 4605523422498301790U, 4603384207141321914U,
1962 13826756243996097722U, 4605523422498301790U,
1963 4595218635031890910U, 4607054494135176056U,
1964 13830426530989951864U, 4595218635031890910U,
1965 4607111255739239816U, 4593688012422887515U,
1966 13817060049277663323U, 4607111255739239816U,
1967 4603694922063032361U, 4605292980606880364U,
1968 13828665017461656172U, 4603694922063032361U,
1969 4605998608960791335U, 4602598930031891166U,
1970 13825970966886666974U, 4605998608960791335U,
1971 4598423001813699022U, 4606863472012527185U,
1972 13830235508867302993U, 4598423001813699022U,
1973 4606719100629313491U, 4599374859150636784U,
1974 13822746896005412592U, 4606719100629313491U,
1975 4601721693286060937U, 4606233055365547081U,
1976 13829605092220322889U, 4601721693286060937U,
1977 4604977468824438271U, 4604079374282302598U,
1978 13827451411137078406U, 4604977468824438271U,
1979 4589744810590291021U, 4607160003989618959U,
1980 13830532040844394767U, 4589744810590291021U,
1981 4607155938267770208U, 4590185751760970393U,
1982 13813557788615746201U, 4607155938267770208U,
1983 4604037525321326463U, 4605013567986435066U,
1984 13828385604841210874U, 4604037525321326463U,
1985 4606208206518262803U, 4601820425647934753U,
1986 13825192462502710561U, 4606208206518262803U,
1987 4599269903251194481U, 4606736437002195879U,
1988 13830108473856971687U, 4599269903251194481U,
1989 4606848731493011465U, 4598529532600161144U,
1990 13821901569454936952U, 4606848731493011465U,
1991 4602502755147763107U, 4606025850160239809U,
1992 13829397887015015617U, 4602502755147763107U,
1993 4605258978359093269U, 4603738491917026584U,
1994 13827110528771802392U, 4605258978359093269U,
1995 4593265590854265407U, 4607118021058468598U,
1996 13830490057913244406U, 4593265590854265407U,
1997 4607045045516813836U, 4595436449949385485U,
1998 13818808486804161293U, 4607045045516813836U,
1999 4603339021357904144U, 4605555245917486022U,
2000 13828927282772261830U, 4603339021357904144U,
2001 4605770164172969910U, 4603017373458244943U,
2002 13826389410313020751U, 4605770164172969910U,
2003 4596954088216812973U, 4606969576261663845U,
2004 13830341613116439653U, 4596954088216812973U,
2005 4606568886807728474U, 4600206446098256018U,
2006 13823578482953031826U, 4606568886807728474U,
2007 4600921238092511730U, 4606420848538580260U,
2008 13829792885393356068U, 4600921238092511730U,
2009 4604679572075463103U, 4604406033021674239U,
2010 13827778069876450047U, 4604679572075463103U,
2011 4581846703643734566U, 4607180341788068727U,
2012 13830552378642844535U, 4581846703643734566U,
2013 4607181359080094673U, 4579996072175835083U,
2014 13803368109030610891U, 4607181359080094673U,
2015 4604445825685214043U, 4604641218080103285U,
2016 13828013254934879093U, 4604445825685214043U,
2017 4606442934727379583U, 4600819913163773071U,
2018 13824191950018548879U, 4606442934727379583U,
2019 4600309328230211502U, 4606548680329491866U,
2020 13829920717184267674U, 4600309328230211502U,
2021 4606981354314050484U, 4596738097012783531U,
2022 13820110133867559339U, 4606981354314050484U,
2023 4603063884010218172U, 4605740310302420207U,
2024 13829112347157196015U, 4603063884010218172U,
2025 4605586791482848547U, 4603293641160266722U,
2026 13826665678015042530U, 4605586791482848547U,
2027 4595654028864046335U, 4607035262954517034U,
2028 13830407299809292842U, 4595654028864046335U,
2029 4607124449686274900U, 4592826452951465409U,
2030 13816198489806241217U, 4607124449686274900U,
2031 4603781852316960384U, 4605224709411790590U,
2032 13828596746266566398U, 4603781852316960384U,
2033 4606052795787882823U, 4602406247776385022U,
2034 13825778284631160830U, 4606052795787882823U,
2035 4598635880488956483U, 4606833664420673202U,
2036 13830205701275449010U, 4598635880488956483U,
2037 4606753451050079834U, 4599164736579548843U,
2038 13822536773434324651U, 4606753451050079834U,
2039 4601918851211878557U, 4606183055233559255U,
2040 13829555092088335063U, 4601918851211878557U,
2041 4605049409688478101U, 4603995455647851249U,
2042 13827367492502627057U, 4605049409688478101U,
2043 4590626485056654602U, 4607151534426937478U,
2044 13830523571281713286U, 4590626485056654602U,
2045 4607163731439411601U, 4589303678145802340U,
2046 13812675715000578148U, 4607163731439411601U,
2047 4604121000955189926U, 4604941113561600762U,
2048 13828313150416376570U, 4604121000955189926U,
2049 4606257600839867033U, 4601622657843474729U,
2050 13824994694698250537U, 4606257600839867033U,
2051 4599479600326345459U, 4606701442584137310U,
2052 13830073479438913118U, 4599479600326345459U,
2053 4606877885424248132U, 4598316292140394014U,
2054 13821688328995169822U, 4606877885424248132U,
2055 4602686793990243041U, 4605971073215153165U,
2056 13829343110069928973U, 4602686793990243041U,
2057 4605326714874986465U, 4603651144395358093U,
2058 13827023181250133901U, 4605326714874986465U,
2059 4593907249284540294U, 4607104153983298999U,
2060 13830476190838074807U, 4593907249284540294U,
2061 4607063608453868552U, 4595000592312171144U,
2062 13818372629166946952U, 4607063608453868552U,
2063 4603429196809300824U, 4605491322423429598U,
2064 13828863359278205406U, 4603429196809300824U,
2065 4605829012964735987U, 4602923807199184054U,
2066 13826295844053959862U, 4605829012964735987U,
2067 4597385183080791534U, 4606945027305114062U,
2068 13830317064159889870U, 4597385183080791534U,
2069 4606608350964852124U, 4599999947619525579U,
2070 13823371984474301387U, 4606608350964852124U,
2071 4601123065313358619U, 4606375745674388705U,
2072 13829747782529164513U, 4601123065313358619U,
2073 4604755543975806820U, 4604325745441780828U,
2074 13827697782296556636U, 4604755543975806820U,
2075 4585023436363055487U, 4607177290141793710U,
2076 13830549326996569518U, 4585023436363055487U,
2077 4607175255902437396U, 4585907115494236537U,
2078 13809279152349012345U, 4607175255902437396U,
2079 4604285253548209224U, 4604793159020491611U,
2080 13828165195875267419U, 4604285253548209224U,
2081 4606352730697093817U, 4601223560006786057U,
2082 13824595596861561865U, 4606352730697093817U,
2083 4599896339047301634U, 4606627607157935956U,
2084 13829999644012711764U, 4599896339047301634U,
2085 4606932257325205256U, 4597600270510262682U,
2086 13820972307365038490U, 4606932257325205256U,
2087 4602876755014813164U, 4605858005670328613U,
2088 13829230042525104421U, 4602876755014813164U,
2089 4605458946901419122U, 4603473988668005304U,
2090 13826846025522781112U, 4605458946901419122U,
2091 4594782329999411347U, 4607072388129742377U,
2092 13830444424984518185U, 4594782329999411347U,
2093 4607096716058023245U, 4594126307716900071U,
2094 13817498344571675879U, 4607096716058023245U,
2095 4603607160562208225U, 4605360179893335444U,
2096 13828732216748111252U, 4603607160562208225U,
2097 4605943243960030558U, 4602734543519989142U,
2098 13826106580374764950U, 4605943243960030558U,
2099 4598209407597805010U, 4606891971185517504U,
2100 13830264008040293312U, 4598209407597805010U,
2101 4606683463531482757U, 4599584122834874440U,
2102 13822956159689650248U, 4606683463531482757U,
2103 4601523323048804569U, 4606281842017099424U,
2104 13829653878871875232U, 4601523323048804569U,
2105 4604904503566677638U, 4604162403772767740U,
2106 13827534440627543548U, 4604904503566677638U,
2107 4588556721781247689U, 4607167120476811757U,
2108 13830539157331587565U, 4588556721781247689U,
2109 4607146792632922887U, 4591066993883984169U,
2110 13814439030738759977U, 4607146792632922887U,
2111 4603953166845776383U, 4605084992581147553U,
2112 13828457029435923361U, 4603953166845776383U,
2113 4606157602458368090U, 4602016966272225497U,
2114 13825389003127001305U, 4606157602458368090U,
2115 4599059363095165615U, 4606770142132396069U,
2116 13830142178987171877U, 4599059363095165615U,
2117 4606818271362779153U, 4598742041476147134U,
2118 13822114078330922942U, 4606818271362779153U,
2119 4602309411551204896U, 4606079444829232727U,
2120 13829451481684008535U, 4602309411551204896U,
2121 4605190175055178825U, 4603825001630339212U,
2122 13827197038485115020U, 4605190175055178825U,
2123 4592387007752762956U, 4607130541380624519U,
2124 13830502578235400327U, 4592387007752762956U,
2125 4607025146816593591U, 4595871363584150300U,
2126 13819243400438926108U, 4607025146816593591U,
2127 4603248068256948438U, 4605618058006716661U,
2128 13828990094861492469U, 4603248068256948438U,
2129 4605710171610479304U, 4603110210506737381U,
2130 13826482247361513189U, 4605710171610479304U,
2131 4596521820799644122U, 4606992800820440327U,
2132 13830364837675216135U, 4596521820799644122U,
2133 4606528158595189433U, 4600411960456200676U,
2134 13823783997310976484U, 4606528158595189433U,
2135 4600718319105833937U, 4606464709641375231U,
2136 13829836746496151039U, 4600718319105833937U,
2137 4604602620643553229U, 4604485382263976838U,
2138 13827857419118752646U, 4604602620643553229U,
2139 4576459225186735875U, 4607182037296057423U,
2140 13830554074150833231U, 4576459225186735875U,
2141 4607182037296057423U, 4576459225186735875U,
2142 13799831262041511683U, 4607182037296057423U,
2143 4604485382263976838U, 4604602620643553229U,
2144 13827974657498329037U, 4604485382263976838U,
2145 4606464709641375231U, 4600718319105833937U,
2146 13824090355960609745U, 4606464709641375231U,
2147 4600411960456200676U, 4606528158595189433U,
2148 13829900195449965241U, 4600411960456200676U,
2149 4606992800820440327U, 4596521820799644122U,
2150 13819893857654419930U, 4606992800820440327U,
2151 4603110210506737381U, 4605710171610479304U,
2152 13829082208465255112U, 4603110210506737381U,
2153 4605618058006716661U, 4603248068256948438U,
2154 13826620105111724246U, 4605618058006716661U,
2155 4595871363584150300U, 4607025146816593591U,
2156 13830397183671369399U, 4595871363584150300U,
2157 4607130541380624519U, 4592387007752762956U,
2158 13815759044607538764U, 4607130541380624519U,
2159 4603825001630339212U, 4605190175055178825U,
2160 13828562211909954633U, 4603825001630339212U,
2161 4606079444829232727U, 4602309411551204896U,
2162 13825681448405980704U, 4606079444829232727U,
2163 4598742041476147134U, 4606818271362779153U,
2164 13830190308217554961U, 4598742041476147134U,
2165 4606770142132396069U, 4599059363095165615U,
2166 13822431399949941423U, 4606770142132396069U,
2167 4602016966272225497U, 4606157602458368090U,
2168 13829529639313143898U, 4602016966272225497U,
2169 4605084992581147553U, 4603953166845776383U,
2170 13827325203700552191U, 4605084992581147553U,
2171 4591066993883984169U, 4607146792632922887U,
2172 13830518829487698695U, 4591066993883984169U,
2173 4607167120476811757U, 4588556721781247689U,
2174 13811928758636023497U, 4607167120476811757U,
2175 4604162403772767740U, 4604904503566677638U,
2176 13828276540421453446U, 4604162403772767740U,
2177 4606281842017099424U, 4601523323048804569U,
2178 13824895359903580377U, 4606281842017099424U,
2179 4599584122834874440U, 4606683463531482757U,
2180 13830055500386258565U, 4599584122834874440U,
2181 4606891971185517504U, 4598209407597805010U,
2182 13821581444452580818U, 4606891971185517504U,
2183 4602734543519989142U, 4605943243960030558U,
2184 13829315280814806366U, 4602734543519989142U,
2185 4605360179893335444U, 4603607160562208225U,
2186 13826979197416984033U, 4605360179893335444U,
2187 4594126307716900071U, 4607096716058023245U,
2188 13830468752912799053U, 4594126307716900071U,
2189 4607072388129742377U, 4594782329999411347U,
2190 13818154366854187155U, 4607072388129742377U,
2191 4603473988668005304U, 4605458946901419122U,
2192 13828830983756194930U, 4603473988668005304U,
2193 4605858005670328613U, 4602876755014813164U,
2194 13826248791869588972U, 4605858005670328613U,
2195 4597600270510262682U, 4606932257325205256U,
2196 13830304294179981064U, 4597600270510262682U,
2197 4606627607157935956U, 4599896339047301634U,
2198 13823268375902077442U, 4606627607157935956U,
2199 4601223560006786057U, 4606352730697093817U,
2200 13829724767551869625U, 4601223560006786057U,
2201 4604793159020491611U, 4604285253548209224U,
2202 13827657290402985032U, 4604793159020491611U,
2203 4585907115494236537U, 4607175255902437396U,
2204 13830547292757213204U, 4585907115494236537U,
2205 4607177290141793710U, 4585023436363055487U,
2206 13808395473217831295U, 4607177290141793710U,
2207 4604325745441780828U, 4604755543975806820U,
2208 13828127580830582628U, 4604325745441780828U,
2209 4606375745674388705U, 4601123065313358619U,
2210 13824495102168134427U, 4606375745674388705U,
2211 4599999947619525579U, 4606608350964852124U,
2212 13829980387819627932U, 4599999947619525579U,
2213 4606945027305114062U, 4597385183080791534U,
2214 13820757219935567342U, 4606945027305114062U,
2215 4602923807199184054U, 4605829012964735987U,
2216 13829201049819511795U, 4602923807199184054U,
2217 4605491322423429598U, 4603429196809300824U,
2218 13826801233664076632U, 4605491322423429598U,
2219 4595000592312171144U, 4607063608453868552U,
2220 13830435645308644360U, 4595000592312171144U,
2221 4607104153983298999U, 4593907249284540294U,
2222 13817279286139316102U, 4607104153983298999U,
2223 4603651144395358093U, 4605326714874986465U,
2224 13828698751729762273U, 4603651144395358093U,
2225 4605971073215153165U, 4602686793990243041U,
2226 13826058830845018849U, 4605971073215153165U,
2227 4598316292140394014U, 4606877885424248132U,
2228 13830249922279023940U, 4598316292140394014U,
2229 4606701442584137310U, 4599479600326345459U,
2230 13822851637181121267U, 4606701442584137310U,
2231 4601622657843474729U, 4606257600839867033U,
2232 13829629637694642841U, 4601622657843474729U,
2233 4604941113561600762U, 4604121000955189926U,
2234 13827493037809965734U, 4604941113561600762U,
2235 4589303678145802340U, 4607163731439411601U,
2236 13830535768294187409U, 4589303678145802340U,
2237 4607151534426937478U, 4590626485056654602U,
2238 13813998521911430410U, 4607151534426937478U,
2239 4603995455647851249U, 4605049409688478101U,
2240 13828421446543253909U, 4603995455647851249U,
2241 4606183055233559255U, 4601918851211878557U,
2242 13825290888066654365U, 4606183055233559255U,
2243 4599164736579548843U, 4606753451050079834U,
2244 13830125487904855642U, 4599164736579548843U,
2245 4606833664420673202U, 4598635880488956483U,
2246 13822007917343732291U, 4606833664420673202U,
2247 4602406247776385022U, 4606052795787882823U,
2248 13829424832642658631U, 4602406247776385022U,
2249 4605224709411790590U, 4603781852316960384U,
2250 13827153889171736192U, 4605224709411790590U,
2251 4592826452951465409U, 4607124449686274900U,
2252 13830496486541050708U, 4592826452951465409U,
2253 4607035262954517034U, 4595654028864046335U,
2254 13819026065718822143U, 4607035262954517034U,
2255 4603293641160266722U, 4605586791482848547U,
2256 13828958828337624355U, 4603293641160266722U,
2257 4605740310302420207U, 4603063884010218172U,
2258 13826435920864993980U, 4605740310302420207U,
2259 4596738097012783531U, 4606981354314050484U,
2260 13830353391168826292U, 4596738097012783531U,
2261 4606548680329491866U, 4600309328230211502U,
2262 13823681365084987310U, 4606548680329491866U,
2263 4600819913163773071U, 4606442934727379583U,
2264 13829814971582155391U, 4600819913163773071U,
2265 4604641218080103285U, 4604445825685214043U,
2266 13827817862539989851U, 4604641218080103285U,
2267 4579996072175835083U, 4607181359080094673U,
2268 13830553395934870481U, 4579996072175835083U,
2269 4607180341788068727U, 4581846703643734566U,
2270 13805218740498510374U, 4607180341788068727U,
2271 4604406033021674239U, 4604679572075463103U,
2272 13828051608930238911U, 4604406033021674239U,
2273 4606420848538580260U, 4600921238092511730U,
2274 13824293274947287538U, 4606420848538580260U,
2275 4600206446098256018U, 4606568886807728474U,
2276 13829940923662504282U, 4600206446098256018U,
2277 4606969576261663845U, 4596954088216812973U,
2278 13820326125071588781U, 4606969576261663845U,
2279 4603017373458244943U, 4605770164172969910U,
2280 13829142201027745718U, 4603017373458244943U,
2281 4605555245917486022U, 4603339021357904144U,
2282 13826711058212679952U, 4605555245917486022U,
2283 4595436449949385485U, 4607045045516813836U,
2284 13830417082371589644U, 4595436449949385485U,
2285 4607118021058468598U, 4593265590854265407U,
2286 13816637627709041215U, 4607118021058468598U,
2287 4603738491917026584U, 4605258978359093269U,
2288 13828631015213869077U, 4603738491917026584U,
2289 4606025850160239809U, 4602502755147763107U,
2290 13825874792002538915U, 4606025850160239809U,
2291 4598529532600161144U, 4606848731493011465U,
2292 13830220768347787273U, 4598529532600161144U,
2293 4606736437002195879U, 4599269903251194481U,
2294 13822641940105970289U, 4606736437002195879U,
2295 4601820425647934753U, 4606208206518262803U,
2296 13829580243373038611U, 4601820425647934753U,
2297 4605013567986435066U, 4604037525321326463U,
2298 13827409562176102271U, 4605013567986435066U,
2299 4590185751760970393U, 4607155938267770208U,
2300 13830527975122546016U, 4590185751760970393U,
2301 4607160003989618959U, 4589744810590291021U,
2302 13813116847445066829U, 4607160003989618959U,
2303 4604079374282302598U, 4604977468824438271U,
2304 13828349505679214079U, 4604079374282302598U,
2305 4606233055365547081U, 4601721693286060937U,
2306 13825093730140836745U, 4606233055365547081U,
2307 4599374859150636784U, 4606719100629313491U,
2308 13830091137484089299U, 4599374859150636784U,
2309 4606863472012527185U, 4598423001813699022U,
2310 13821795038668474830U, 4606863472012527185U,
2311 4602598930031891166U, 4605998608960791335U,
2312 13829370645815567143U, 4602598930031891166U,
2313 4605292980606880364U, 4603694922063032361U,
2314 13827066958917808169U, 4605292980606880364U,
2315 4593688012422887515U, 4607111255739239816U,
2316 13830483292594015624U, 4593688012422887515U,
2317 4607054494135176056U, 4595218635031890910U,
2318 13818590671886666718U, 4607054494135176056U,
2319 4603384207141321914U, 4605523422498301790U,
2320 13828895459353077598U, 4603384207141321914U,
2321 4605799732098147061U, 4602970680601913687U,
2322 13826342717456689495U, 4605799732098147061U,
2323 4597169786279785693U, 4606957467106717424U,
2324 13830329503961493232U, 4597169786279785693U,
2325 4606588777269136769U, 4600103317933788342U,
2326 13823475354788564150U, 4606588777269136769U,
2327 4601022290077223616U, 4606398451906509788U,
2328 13829770488761285596U, 4601022290077223616U,
2329 4604717681185626434U, 4604366005771528720U,
2330 13827738042626304528U, 4604717681185626434U,
2331 4583614727651146525U, 4607178985458280057U,
2332 13830551022313055865U, 4583614727651146525U,
2333 4607172882816799076U, 4586790578280679046U,
2334 13810162615135454854U, 4607172882816799076U,
2335 4604244531615310815U, 4604830524903495634U,
2336 13828202561758271442U, 4604244531615310815U,
2337 4606329407841126011U, 4601323770373937522U,
2338 13824695807228713330U, 4606329407841126011U,
2339 4599792496117920694U, 4606646545123403481U,
2340 13830018581978179289U, 4599792496117920694U,
2341 4606919157647773535U, 4597815040470278984U,
2342 13821187077325054792U, 4606919157647773535U,
2343 4602829525820289164U, 4605886709123365959U,
2344 13829258745978141767U, 4602829525820289164U,
2345 4605426297151190466U, 4603518581031047189U,
2346 13826890617885822997U, 4605426297151190466U,
2347 4594563856311064231U, 4607080832832247697U,
2348 13830452869687023505U, 4594563856311064231U,
2349 4607088942243446236U, 4594345179472540681U,
2350 13817717216327316489U, 4607088942243446236U,
2351 4603562972219549215U, 4605393374401988274U,
2352 13828765411256764082U, 4603562972219549215U,
2353 4605915122243179241U, 4602782121393764535U,
2354 13826154158248540343U, 4605915122243179241U,
2355 4598029484874872834U, 4606905728766014348U,
2356 13830277765620790156U, 4598029484874872834U,
2357 4606665164148251002U, 4599688422741010356U,
2358 13823060459595786164U, 4606665164148251002U,
2359 4601423692641949331U, 4606305777984577632U,
2360 13829677814839353440U, 4601423692641949331U,
2361 4604867640218014515U, 4604203581176243359U,
2362 13827575618031019167U, 4604867640218014515U,
2363 4587673791460508439U, 4607170170974224083U,
2364 13830542207828999891U, 4587673791460508439U,
2365 4607141713064252300U, 4591507261658050721U,
2366 13814879298512826529U, 4607141713064252300U,
2367 4603910660507251362U, 4605120315324767624U,
2368 13828492352179543432U, 4603910660507251362U,
2369 4606131849150971908U, 4602114767134999006U,
2370 13825486803989774814U, 4606131849150971908U,
2371 4598953786765296928U, 4606786509620734768U,
2372 13830158546475510576U, 4598953786765296928U,
2373 4606802552898869248U, 4598848011564831930U,
2374 13822220048419607738U, 4606802552898869248U,
2375 4602212250118051877U, 4606105796280968177U,
2376 13829477833135743985U, 4602212250118051877U,
2377 4605155376589456981U, 4603867938232615808U,
2378 13827239975087391616U, 4605155376589456981U,
2379 4591947271803021404U, 4607136295912168606U,
2380 13830508332766944414U, 4591947271803021404U,
2381 4607014697483910382U, 4596088445927168004U,
2382 13819460482781943812U, 4607014697483910382U,
2383 4603202304363743346U, 4605649044311923410U,
2384 13829021081166699218U, 4603202304363743346U,
2385 4605679749231851918U, 4603156351203636159U,
2386 13826528388058411967U, 4605679749231851918U,
2387 4596305267720071930U, 4607003915349878877U,
2388 13830375952204654685U, 4596305267720071930U,
2389 4606507322377452870U, 4600514338912178239U,
2390 13823886375766954047U, 4606507322377452870U,
2391 4600616459743653188U, 4606486172460753999U,
2392 13829858209315529807U, 4600616459743653188U,
2393 4604563781218984604U, 4604524701268679793U,
2394 13827896738123455601U, 4604563781218984604U,
2395 4569220649180767418U, 4607182376410422530U,
2396 13830554413265198338U, 4569220649180767418U
2397 };
2398
2399 const fpr fpr_p2_tab[] = {
2400 4611686018427387904U,
2401 4607182418800017408U,
2402 4602678819172646912U,
2403 4598175219545276416U,
2404 4593671619917905920U,
2405 4589168020290535424U,
2406 4584664420663164928U,
2407 4580160821035794432U,
2408 4575657221408423936U,
2409 4571153621781053440U,
2410 4566650022153682944U
2411 };
2412
2413 #elif FALCON_FPNATIVE // yyyFPEMU+0 yyyFPNATIVE+1
2414
2415 const fpr fpr_gm_tab[] = {
2416 {0}, {0}, /* unused */
2417 {-0.000000000000000000000000000}, { 1.000000000000000000000000000},
2418 { 0.707106781186547524400844362}, { 0.707106781186547524400844362},
2419 {-0.707106781186547524400844362}, { 0.707106781186547524400844362},
2420 { 0.923879532511286756128183189}, { 0.382683432365089771728459984},
2421 {-0.382683432365089771728459984}, { 0.923879532511286756128183189},
2422 { 0.382683432365089771728459984}, { 0.923879532511286756128183189},
2423 {-0.923879532511286756128183189}, { 0.382683432365089771728459984},
2424 { 0.980785280403230449126182236}, { 0.195090322016128267848284868},
2425 {-0.195090322016128267848284868}, { 0.980785280403230449126182236},
2426 { 0.555570233019602224742830814}, { 0.831469612302545237078788378},
2427 {-0.831469612302545237078788378}, { 0.555570233019602224742830814},
2428 { 0.831469612302545237078788378}, { 0.555570233019602224742830814},
2429 {-0.555570233019602224742830814}, { 0.831469612302545237078788378},
2430 { 0.195090322016128267848284868}, { 0.980785280403230449126182236},
2431 {-0.980785280403230449126182236}, { 0.195090322016128267848284868},
2432 { 0.995184726672196886244836953}, { 0.098017140329560601994195564},
2433 {-0.098017140329560601994195564}, { 0.995184726672196886244836953},
2434 { 0.634393284163645498215171613}, { 0.773010453362736960810906610},
2435 {-0.773010453362736960810906610}, { 0.634393284163645498215171613},
2436 { 0.881921264348355029712756864}, { 0.471396736825997648556387626},
2437 {-0.471396736825997648556387626}, { 0.881921264348355029712756864},
2438 { 0.290284677254462367636192376}, { 0.956940335732208864935797887},
2439 {-0.956940335732208864935797887}, { 0.290284677254462367636192376},
2440 { 0.956940335732208864935797887}, { 0.290284677254462367636192376},
2441 {-0.290284677254462367636192376}, { 0.956940335732208864935797887},
2442 { 0.471396736825997648556387626}, { 0.881921264348355029712756864},
2443 {-0.881921264348355029712756864}, { 0.471396736825997648556387626},
2444 { 0.773010453362736960810906610}, { 0.634393284163645498215171613},
2445 {-0.634393284163645498215171613}, { 0.773010453362736960810906610},
2446 { 0.098017140329560601994195564}, { 0.995184726672196886244836953},
2447 {-0.995184726672196886244836953}, { 0.098017140329560601994195564},
2448 { 0.998795456205172392714771605}, { 0.049067674327418014254954977},
2449 {-0.049067674327418014254954977}, { 0.998795456205172392714771605},
2450 { 0.671558954847018400625376850}, { 0.740951125354959091175616897},
2451 {-0.740951125354959091175616897}, { 0.671558954847018400625376850},
2452 { 0.903989293123443331586200297}, { 0.427555093430282094320966857},
2453 {-0.427555093430282094320966857}, { 0.903989293123443331586200297},
2454 { 0.336889853392220050689253213}, { 0.941544065183020778412509403},
2455 {-0.941544065183020778412509403}, { 0.336889853392220050689253213},
2456 { 0.970031253194543992603984207}, { 0.242980179903263889948274162},
2457 {-0.242980179903263889948274162}, { 0.970031253194543992603984207},
2458 { 0.514102744193221726593693839}, { 0.857728610000272069902269984},
2459 {-0.857728610000272069902269984}, { 0.514102744193221726593693839},
2460 { 0.803207531480644909806676513}, { 0.595699304492433343467036529},
2461 {-0.595699304492433343467036529}, { 0.803207531480644909806676513},
2462 { 0.146730474455361751658850130}, { 0.989176509964780973451673738},
2463 {-0.989176509964780973451673738}, { 0.146730474455361751658850130},
2464 { 0.989176509964780973451673738}, { 0.146730474455361751658850130},
2465 {-0.146730474455361751658850130}, { 0.989176509964780973451673738},
2466 { 0.595699304492433343467036529}, { 0.803207531480644909806676513},
2467 {-0.803207531480644909806676513}, { 0.595699304492433343467036529},
2468 { 0.857728610000272069902269984}, { 0.514102744193221726593693839},
2469 {-0.514102744193221726593693839}, { 0.857728610000272069902269984},
2470 { 0.242980179903263889948274162}, { 0.970031253194543992603984207},
2471 {-0.970031253194543992603984207}, { 0.242980179903263889948274162},
2472 { 0.941544065183020778412509403}, { 0.336889853392220050689253213},
2473 {-0.336889853392220050689253213}, { 0.941544065183020778412509403},
2474 { 0.427555093430282094320966857}, { 0.903989293123443331586200297},
2475 {-0.903989293123443331586200297}, { 0.427555093430282094320966857},
2476 { 0.740951125354959091175616897}, { 0.671558954847018400625376850},
2477 {-0.671558954847018400625376850}, { 0.740951125354959091175616897},
2478 { 0.049067674327418014254954977}, { 0.998795456205172392714771605},
2479 {-0.998795456205172392714771605}, { 0.049067674327418014254954977},
2480 { 0.999698818696204220115765650}, { 0.024541228522912288031734529},
2481 {-0.024541228522912288031734529}, { 0.999698818696204220115765650},
2482 { 0.689540544737066924616730630}, { 0.724247082951466920941069243},
2483 {-0.724247082951466920941069243}, { 0.689540544737066924616730630},
2484 { 0.914209755703530654635014829}, { 0.405241314004989870908481306},
2485 {-0.405241314004989870908481306}, { 0.914209755703530654635014829},
2486 { 0.359895036534988148775104572}, { 0.932992798834738887711660256},
2487 {-0.932992798834738887711660256}, { 0.359895036534988148775104572},
2488 { 0.975702130038528544460395766}, { 0.219101240156869797227737547},
2489 {-0.219101240156869797227737547}, { 0.975702130038528544460395766},
2490 { 0.534997619887097210663076905}, { 0.844853565249707073259571205},
2491 {-0.844853565249707073259571205}, { 0.534997619887097210663076905},
2492 { 0.817584813151583696504920884}, { 0.575808191417845300745972454},
2493 {-0.575808191417845300745972454}, { 0.817584813151583696504920884},
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3415 {-0.956045251349996443270479823}, { 0.293219162694258650606608599},
3416 { 0.957826413027532890321037029}, { 0.287347459544729526477331841},
3417 {-0.287347459544729526477331841}, { 0.957826413027532890321037029},
3418 { 0.474100214650550014398580015}, { 0.880470889052160770806542929},
3419 {-0.880470889052160770806542929}, { 0.474100214650550014398580015},
3420 { 0.774953106594873878359129282}, { 0.632018735939809021909403706},
3421 {-0.632018735939809021909403706}, { 0.774953106594873878359129282},
3422 { 0.101069862754827824987887585}, { 0.994879330794805620591166107},
3423 {-0.994879330794805620591166107}, { 0.101069862754827824987887585},
3424 { 0.981379193313754574318224190}, { 0.192080397049892441679288205},
3425 {-0.192080397049892441679288205}, { 0.981379193313754574318224190},
3426 { 0.558118531220556115693702964}, { 0.829761233794523042469023765},
3427 {-0.829761233794523042469023765}, { 0.558118531220556115693702964},
3428 { 0.833170164701913186439915922}, { 0.553016705580027531764226988},
3429 {-0.553016705580027531764226988}, { 0.833170164701913186439915922},
3430 { 0.198098410717953586179324918}, { 0.980182135968117392690210009},
3431 {-0.980182135968117392690210009}, { 0.198098410717953586179324918},
3432 { 0.925049240782677590302371869}, { 0.379847208924051170576281147},
3433 {-0.379847208924051170576281147}, { 0.925049240782677590302371869},
3434 { 0.385516053843918864075607949}, { 0.922701128333878570437264227},
3435 {-0.922701128333878570437264227}, { 0.385516053843918864075607949},
3436 { 0.709272826438865651316533772}, { 0.704934080375904908852523758},
3437 {-0.704934080375904908852523758}, { 0.709272826438865651316533772},
3438 { 0.003067956762965976270145365}, { 0.999995293809576171511580126},
3439 {-0.999995293809576171511580126}, { 0.003067956762965976270145365}
3440 };
3441
3442 const fpr fpr_p2_tab[] = {
3443 { 2.00000000000 },
3444 { 1.00000000000 },
3445 { 0.50000000000 },
3446 { 0.25000000000 },
3447 { 0.12500000000 },
3448 { 0.06250000000 },
3449 { 0.03125000000 },
3450 { 0.01562500000 },
3451 { 0.00781250000 },
3452 { 0.00390625000 },
3453 { 0.00195312500 }
3454 };
3455
3456 #else // yyyFPNATIVE+0 yyyFPEMU+0
3457
3458 #error No FP implementation selected
3459
3460 #endif // yyyFPNATIVE- yyyFPEMU-